Patents by Inventor Kanta WATANABE

Kanta WATANABE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240004366
    Abstract: A device that creates information related to a machining program includes a numerical control device, a PC in which machining program creation software is installed, and a dedicated device that is an emulator for the numerical control device. The numerical control device acquires setup information required for a setup operation from the information related to the machining program of a machine tool controlled by the numerical control device and acquires setup basic information from information registered in a device configured to execute the machining program of the machine tool. Setup support information is then generated from the setup information and the setup basic information. Accordingly, the numerical control device supports a setup operation of the machining program by using the acquired setup information and the generated setup support information.
    Type: Application
    Filed: January 28, 2022
    Publication date: January 4, 2024
    Applicant: Fanuc Corporation
    Inventors: Kanta Watanabe, Kazuhiro Hirauchi
  • Publication number: 20230013725
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers, a vertical layer stack located over the alternating stack, and including multiple levels of vertically interlaced drain select electrodes and drain-select-level insulating layers, a first insulating layer located between the alternating stack and the vertical layer stack, the first insulating layer having a thickness which is greater than a thickness of the respective insulating layers and the respective drain-select-level insulating layers, drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures, memory openings vertically extending through the vertical layer stack, the first insulating layer, and the alternating stack, and memory opening fill structures located in the memory openings and i
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Inventors: Kanta WATANABE, Yanli ZHANG