Patents by Inventor Kanu Chadha
Kanu Chadha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8498243Abstract: An apparatus and method for non-exclusive multiplexing of at least one active control channel comprising preparing the at least one active control channel for transmission in a next frame using a transmitter data processor; assessing channel robustness of the at least one active control channel based on a channel robustness threshold; and if the channel robustness threshold is not met, performing constellation control or power control on the at least one active control channel which is active prior to transmitting the at least one active control channel; or if the channel robustness threshold is met, transmitting the at least one active control channel using a transmitter.Type: GrantFiled: June 9, 2009Date of Patent: July 30, 2013Assignee: QUALCOMM IncorporatedInventors: Ming-Chang Tsai, Jigneshkumar P. Shah, Kanu Chadha
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Patent number: 8072347Abstract: A method for determining electrical condition of a wired drill pipe includes inducing an electromagnetic field in at least one joint of wired drill pipe. Voltages induced by electrical current flowing in at least one electrical conductor in the at least one wired drill pipe joint are detected. The electrical current is induced by the induced electromagnetic field. The electrical condition is determined from the detected voltages.Type: GrantFiled: December 29, 2006Date of Patent: December 6, 2011Assignee: Intelliserv, LLC.Inventors: David Santoso, Dudi Rendusara, Hiroshi Nakajima, Kanu Chadha, Raghu Madhavan, Lise Hvatum
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Patent number: 7957343Abstract: A method is provided for compensating for clock drift error and movement error of an access terminal. A forward link error is obtained that is attributable to at least a first error (e.g., clock drift error) component and a second error (e.g., movement error) component. The first error component and the second error component are estimated based on the obtained forward link error. A receive clock of the access terminal is compensated based on a combination of the first error component and the second error component. A transmit clock of the access terminal is compensated based on a difference between the first error component and the second error component. The forward link error may include a timing synchronization error between the access terminal and an access point as well as a frequency synchronization error between a forward link frequency and a baseband reference frequency.Type: GrantFiled: October 30, 2008Date of Patent: June 7, 2011Assignee: QUALCOMM IncorporatedInventors: Ming-Chang Tsai, Jigneshkumar Shah, Kanu Chadha
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Patent number: 7894325Abstract: The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplexing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.Type: GrantFiled: November 14, 2008Date of Patent: February 22, 2011Assignee: Edgewater Computer Systems, Inc.Inventors: Kanu Chadha, Manish Bhardwaj
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Patent number: 7733764Abstract: Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.Type: GrantFiled: December 9, 2003Date of Patent: June 8, 2010Assignee: Edgewater Computer Systems, Inc.Inventors: Maneesh Soni, Kanu Chadha, Manish Bhardwaj
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Publication number: 20090310536Abstract: An apparatus and method for non-exclusive multiplexing of at least one active control channel comprising preparing the at least one active control channel for transmission in a next frame using a transmitter data processor; assessing channel robustness of the at least one active control channel based on a channel robustness threshold; and if the channel robustness threshold is not met, performing constellation control or power control on the at least one active control channel which is active prior to transmitting the at least one active control channel; or if the channel robustness threshold is met, transmitting the at least one active control channel using a transmitter.Type: ApplicationFiled: June 9, 2009Publication date: December 17, 2009Applicant: QUALCOMM IncorporatedInventors: Ming-Chang Tsai, Jigneshkumar P. Shah, Kanu Chadha
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Publication number: 20090225662Abstract: A method is provided for compensating for clock drift error and movement error of an access terminal. A forward link error is obtained that is attributable to at least a first error (e.g., clock drift error) component and a second error (e.g., movement error) component. The first error component and the second error component are estimated based on the obtained forward link error. A receive clock of the access terminal is compensated based on a combination of the first error component and the second error component. A transmit clock of the access terminal is compensated based on a difference between the first error component and the second error component. The forward link error may include a timing synchronization error between the access terminal and an access point as well as a frequency synchronization error between a forward link frequency and a baseband reference frequency.Type: ApplicationFiled: October 30, 2008Publication date: September 10, 2009Applicant: QUALCOMM IncorporatedInventors: Ming-Chang Tsai, Jigneshkumar Shah, Kanu Chadha
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Publication number: 20090073869Abstract: The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplixing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.Type: ApplicationFiled: November 14, 2008Publication date: March 19, 2009Applicant: Edgewater Computer Systems, Inc.Inventors: Kanu Chadha, Manish Bhardwai
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Patent number: 7453792Abstract: The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplexing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.Type: GrantFiled: November 14, 2003Date of Patent: November 18, 2008Assignee: Edgewater Computer Systems, Inc.Inventors: Kanu Chadha, Manish Bhardwaj
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Patent number: 7415059Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).Type: GrantFiled: November 13, 2003Date of Patent: August 19, 2008Assignee: Edgewater Computer Systems, Inc.Inventors: Kanu Chadha, Maneesh Soni, Manish Bhardwaj
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Publication number: 20080158005Abstract: A method for determining electrical condition of a wired drill pipe includes inducing an electromagnetic field in at least one joint of wired drill pipe. Voltages induced by electrical current flowing in at least one electrical conductor in the at least one wired drill pipe joint are detected. The electrical current is induced by the induced electromagnetic field. The electrical condition is determined from the detected voltages.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: David Santoso, Dudi Rendusara, Hiroshi Nakajima, Kanu Chadha, Raghu Madhavan, Lise Hvatum
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Publication number: 20070063865Abstract: A telemetry kit for passing signals between a surface control unit and a downhole tool via a wired drill pipe telemetry system is provided. The kit has a first terminal operatively connectable to the wired drill pipe telemetry system for communication therewith, a second terminal operatively connectable to one of the surface control unit and the downhole tool for communication therewith and at least one transmission element operatively connecting the first terminal to the second terminal. The telemetry kit is positionable such that the telemetry kit traverses at least a portion of the downhole tool and/or the wired drill pipe telemetry system whereby the signals bypass the portion thereof.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Inventors: Raghu Madhavan, David Santoso, Kanu Chadha, Lise Hvatum
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Publication number: 20040174810Abstract: Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.Type: ApplicationFiled: December 9, 2003Publication date: September 9, 2004Applicant: Engim, Inc.Inventors: Maneesh Soni, Kanu Chadha, Manish Bhardwaj
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Publication number: 20040170237Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).Type: ApplicationFiled: November 13, 2003Publication date: September 2, 2004Applicant: Engim, Inc.Inventors: Kanu Chadha, Maneesh Soni, Manish Bhardwaj
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Publication number: 20040156309Abstract: The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplixing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.Type: ApplicationFiled: November 14, 2003Publication date: August 12, 2004Applicant: Engim, Inc.Inventors: Kanu Chadha, Manish Bhardwaj
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Publication number: 20040152418Abstract: A unified digital front end filtering circuit is described for IEEE 802.11g protocol compliant systems. The front end uses polyphase rate conversion filters cascaded with channel extraction and pulse shaping filters to accommodate the different sampling rate requirements for orthogonal frequency division multiplexing (OFDM) and direct sequence spread spectrum (DSSS) modulation, which have to be supported simultaneously, without using separate analog front ends.Type: ApplicationFiled: November 6, 2003Publication date: August 5, 2004Applicant: Engim, Inc.Inventors: Amit Sinha, Manish Bhardwaj, Kanu Chadha