Patents by Inventor Kanwal Singh

Kanwal Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor interconnect structures
    Patent number: 9064872
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Kanwal Singh, James Clarke, Alan Myers
  • SEMICONDUCTOR INTERCONNECT STRUCTURES
    Publication number: 20140312508
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 23, 2014
    Inventors: Boyan Boyanov, Kanwal Singh, James Clarke, Alan Myers
  • Semiconductor interconnect structures
    Patent number: 8772938
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Kanwal Singh, James Clarke, Alan Myers
  • SEMICONDUCTOR INTERCONNECT STRUCTURES
    Publication number: 20140151893
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Inventors: Boyan Boyanov, Kanwal Singh, James Clarke, Alan Myers