Abstract: Apparatus and associated methods relate to mitigating data-stream dropout in a serial data-stream. A time-sequence of messages of the serial data-stream is received, each containing a data packet communicating an action. Validity of each of the time-sequence of messages received is determined. After receiving each valid message, a plurality of future actions is created based at least in part on the valid message received. The plurality of future actions corresponds to a plurality of future data packets of the time-sequence of messages. After receiving each valid message, the action communicated in the valid message received is performed. After receiving each invalid messages, a next one of the set of sequential future actions created is instead used in place of any action communicated in the data packet of the invalid message received.

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the primary winding, and an analog-to-digital converter electrically connected to the secondary winding. A control module is operatively connected to analog-to-digital converter and is responsive to instructions to apply an excitation voltage with an oscillating waveform to the primary winding, induce a secondary voltage using the secondary winding using the excitation voltage, and acquire a plurality of voltage measurements from the secondary winding separated by a time interval corresponding to ?/3 of the excitation voltage oscillating waveform.

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A modular embedded controller includes an enclosure with an external interface, a generic motherboard, and an external device-specific input/output daughterboard. The generic motherboard has a supervisory processor and a plurality of daughterboard seats and is supported in the enclosure. The external device-specific input/output daughterboard is supported in one of the daughterboard seats, connects the external interface to the motherboard supervisory processor, and has an input/output processor translate data communicated between the motherboard supervisory processor and a device connected to the external interface. Embedded engine controllers and gas turbine engines with embedded controllers are also described.

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the primary winding, and an analog-to-digital converter electrically connected to the secondary winding. A control module is operatively connected to analog-to-digital converter and is responsive to instructions to apply an excitation voltage with an oscillating waveform to the primary winding, induce a secondary voltage using the secondary winding using the excitation voltage, and acquire a plurality of voltage measurements from the secondary winding separated by a time interval corresponding to ?/3 of the excitation voltage oscillating waveform.

Abstract: A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed.

Abstract: A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed.

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power.

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time.

Abstract: A method for diagnosing hardware failures in a data processing system includes a configuring a portion of a programmable logic device to create a state machine. The state machine tests a communication bus and a plurality of component devices connected by the communication bus and identifies the test failures. The state machine communicates the test information to external test equipment. The communication bus is used in the operation of the data processing system and the testing includes tests at full clock speed of the data processing system.

Abstract: A method for diagnosing hardware failures in a data processing system includes a configuring a portion of a programmable logic device to create a state machine. The state machine tests a communication bus and a plurality of component devices connected by the communication bus and identifies the test failures. The state machine communicates the test information to external test equipment. The communication bus is used in the operation of the data processing system and the testing includes tests at full clock speed of the data processing system.