Abstract: Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.

Abstract: Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.

Abstract: A method and system for synchronous page addressing in a data packet switch is provided. Within the packet switch, separate devices are responsible for storing a portion of a received data packet, and thus a view of used memory addresses seen by one device matches that seen by the others. Each device uses the same order of memory addresses to write data so that bytes of data are stored as a linked-list of pages. Maintaining the same sequence of page requests and sequence of free-page addresses to which to write these pages ensures consistent addressing of the portions of the data packet.

Abstract: A cache implements bank-by-bank locking to keep critical code from being flushed out of the cache. A register is maintained to rank the banks from the most recently used to the least recently used. Ordinarily, when code needs to be moved into the cache, the least recently used bank is flushed, the code is moved into that bank, and the register is updated to identify that bank as the most recently used. However, if a bank is designated in a bypass vector as being locked, that bank is bypassed in the maintenance of the register and is thus never identified as the bank to be flushed.

Abstract: Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.

Abstract: A method for simultaneous testing of individual components in multiple three phase inverters, each connected to a common source of direct current electric power and being coupled to supply power to a respective one of a plurality of three phase loads, involves the steps of monitoring the voltage applied to the inverters and the current at each output phase terminal while gating each switching device in each inverter momentarily into conduction in sequence from a first switching device in a first phase to a last switching device in a third phase until an input voltage drop or an output current is detected. In response to a detected voltage drop, the sequence of gating is interrupted and advanced forward to the next occurring phase. If phase current is detected in any phase during gating, the inverter generating the current is disabled.

Abstract: A device for creating and analyzing larger symbolic representations without the limitations imposed by available resources of previous devices is disclosed. More specifically, a debugger for debugging a symbolic representation of a program is disclosed. The debugger comprising means for inputting a set of characteristics, means for linking the set of characteristics to the symbolic representation, means for identifying a first portion of the symbolic representation mutually exclusive from the set of characteristics, and means for analyzing a second portion of the symbolic representation for the set of characteristics wherein the second portion being mutually exclusive from the first portion. A method of debugging programs using the debugger, in addition to the resultant debugged program, is also disclosed.