Abstract: This application relates to a data storage method, a reading method, an apparatus, a storage medium, and a program product. The data storage method is applied to a processor and includes: (S1) obtaining event data; (S2) processing the event data, to obtain a plurality of data blocks and a plurality of corresponding metadata blocks, where each data block includes a part of processed event data, and each metadata block includes a start time, an end time, a quantity, and a compression manner of event data in a data block corresponding to the metadata block, and a storage address of the data block; and (S3) storing the plurality of data blocks into a first storage area, and storing the plurality of metadata blocks into a second storage area.

Abstract: A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

Abstract: A spiking neural network circuit implemented in a chip includes a plurality of decompression modules and a calculation module. The plurality of decompression modules are configured to obtain a plurality of weight values in a compressed weight matrix and identifiers of a plurality of corresponding output neurons based on information about a plurality of input neurons. Each of the plurality of decompression modules is configured to obtain weight values with a same row number in the compressed weight matrix and identifiers of a plurality of output neurons corresponding to the weight values with the same row number. Each row of the compressed weight matrix has a same quantity of non-zero weight values. Each row of weight values corresponds to one input neuron. The calculation module then determines corresponding membrane voltages of the plurality of output neurons based on the plurality of weight values.

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Abstract: A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

Abstract: A method for data processing in a neural network system and a neural network system are provided. The method includes: inputting training data into a neural network system to obtain first output data, and adjusting, based on a deviation between the first output data and target output data, a weight value stored in at least one in-memory computing unit in some neural network arrays in a plurality of neural network arrays in the neural network system using parallel acceleration. The some neural network arrays are configured to implement computing of some neural network layers in the neural network system. The method may improve performance and recognition accuracy of the neural network system.

Abstract: This application provides a unit, including a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are connected to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be connected and disconnected; the resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor; where the resistance of the memristor is used to indicate the first data stored by the memristor; and when a voltage used to indicate second data is input to a second electrode of the first transistor which is configured to output a computation result of the first data and the second data from a third electrode of the first transistor.

Abstract: This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1T1R. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Abstract: A memory refresh method is applied to a computer system including a memory controller and a dynamic random access memory (DRAM). The memory controller receives access requests including access requests for accessing a first rank of multiple ranks in the DRAM. When a quantity of the access requests for accessing the first rank is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. The first rank may be refreshed in time even if the first rank cannot be in an idle state.

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.