Abstract: A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, an epitaxial layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, epitaxialan layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

Abstract: A fabricating method of a shielded gate MOSFET is provided, includes the steps of forming a semiconductor substrate having a trench, forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench, forming a source polycrystalline silicon region in the trench, forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer, depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region, forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench, forming a gate polycrystalline silicon region in the trench, and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A fabricating method of a shielded gate MOSFET is provided, including steps of: forming a semiconductor substrate having a trench; forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench; forming a source polycrystalline silicon region in the trench; forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer; depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region; forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench; forming a gate polycrystalline silicon region in the trench; and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A power metal-oxide-semiconductor (MOS) device is provided. The power MOS device is formed on a semiconductor substrate and includes an active region and a breakdown generated region. The active region includes a plurality of P-type doping regions and a plurality of N-type doping region alternatively arrayed between a source electrode and a drain electrode, and also includes a plurality of gate structures for controlling the conductive state of the active region. The breakdown generated region includes at least one P-type doping region and at least one N-type doping region alternatively arrayed between a source electrode and a drain electrode, and the breakdown voltage of the breakdown generated region is smaller than that of the active region.

Abstract: A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal.

Abstract: A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily doped region is provided. The trench is formed in the base. The heavily doped polysilicon structure is formed in the lower portion of the trench. At least a side surface of the heavily doped polysilicon structure touches the naked base. The polysilicon gate is located in the upper portion of the trench. The gate dielectric layer is interposed between the polysilicon gate and the heavily doped polysilicon structure. The dopants in the heavily doped polysilicon structure are diffused outward to form a heavily doped region.

Abstract: A fabrication method of trench power semiconductor structure with high switching speed is provided. An epitaxial layer with a first conductivity type is formed on a substrate. Then, gate structures are formed in the epitaxial layer. A shallow doped region with the first conductivity type is formed in the surface layer of the epitaxial layer. After that, a shielding structure is formed on the shallow doped region. Then, wells with a second conductivity type are formed in the epitaxial layer by using the shielding structure as an implantation mask. Finally, a source doped region with the first conductivity type is formed on the surface of the well. The doping concentration of the shallow doped layer is smaller than that of the source doped region and the well. The doping concentration of the shallow doped layer is larger than that of the epitaxial layer.

Abstract: The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.