Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A computer system including a central processing unit (CPU), a chipset, a first bus, a second bus, a first memory, a second memory, and a logic control circuit is disclosed. The chipset is coupled to the CPU. The first bus and the second bus are respectively coupled to the chipset. The first memory is coupled to the chipset through the first bus for storing a first basic input output system (BIOS). The second memory is coupled to the chipset through the second bus for storing a second basic input output system (BIOS). The logic control circuit detects a state of the first bus and controls the chipset to select to access the first memory through the first bus or select to access the second memory through the second bus according to the state of the first bus.

Abstract: A profile control system for controlling a profile of a polishing pad, adapted in a chemical mechanical polishing (CMP) apparatus comprises: a polishing pad, a polishing table, a polishing head, and a conditioner, wherein the polishing pad has a transparent region. The control system includes at least one illuminant, a detector and a processor. The illuminant is in the polishing table and corresponds to the transparent region of the polishing pad. The detector is over the polishing pad to detect the light from the illuminant passing through the transparent region of the polishing pad. The processor is adapted to determine the thickness of the polishing pad according to the light detected by the detector and transmits a processing signal to the conditioner for adjusting processing recipes of the conditioner. Therefore, it is possible to obtain a polishing pad of a desired profile and the variations of the uniformity of the wafers can be reduced.