Abstract: A semiconductor device comprising a memory cell matrix array wherein transistors formed on the outer edge of the memory cell matrix array are inferior in performance compared to the transistors comprising the operating memory cell matrix array because their transistor active regions shrink during semiconductor device fabrication. To avoid this problem, a dummy region is formed around the operating memory cell matrix array. The dummy region contains impurity regions formed at substantially the same density as the transistors comprising the operating memory cell matrix array. Thus, the transistors located on the outer edge of the operating memory cell matrix array function in the same manner as transistors formed within the operating memory cell matrix array. As a result, all the transistors of the operating memory cell matrix array have uniform performance.