Patents by Inventor Kaori Sumitomo

Kaori Sumitomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352392
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Inventors: Hiroaki MATSUBARA, Kaori SUMITOMO, Maki MOROI, Naoki KINOSHITA
  • Patent number: 11735511
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: August 22, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Hiroaki Matsubara, Kaori Sumitomo, Maki Moroi, Naoki Kinoshita
  • Publication number: 20220020678
    Abstract: A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 20, 2022
    Inventors: Hiroaki MATSUBARA, Kaori SUMITOMO, Maki MOROI, Naoki KINOSHITA
  • Patent number: 9230937
    Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
  • Patent number: 8415245
    Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuki Takata, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
  • Publication number: 20120286427
    Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Inventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
  • Publication number: 20110057299
    Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Inventors: Yasuki TAKATA, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa