Abstract: A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.

Abstract: A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.

Abstract: Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.

Abstract: A semiconductor device has an insulated gate transistor provided with a semiconductor substrate and a gate electrode arranged on the semiconductor substrate via a gate insulating film. The gate electrode includes an electrically-conductive buffer film for preventing any damage, which would occur if a main gate electrode portion were formed directly over the gate insulating film, and the main gate electrode portion formed over the buffer film. A fabrication process for the semiconductor device is also disclosed.

Abstract: A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film containing hafnium and silicon.

Abstract: A semiconductor device has an insulated gate transistor provided with a semiconductor substrate and a gate electrode arranged on the semiconductor substrate via a gate insulating film. The gate electrode includes an electrically-conductive buffer film for preventing any damage, which would occur if a main gate electrode portion were formed directly over the gate insulating film, and the main gate electrode portion formed over the buffer film. A fabrication process for the semiconductor device is also disclosed.

Abstract: Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.

Abstract: Electric conductivity is enhanced without causing coagulation or precipitation of polishing abrasive grains. In addition, good planarization is realized without inducing defects in a metallic film or a wiring which are to be polished. In an electropolishing method for planarizing the surface of a metallic film to be polished by moving a polishing pad (15) in sliding contact with the metallic film surface while oxidizing the metallic film surface through an electrolytic action in an electropolishing liquid E, the electropolishing liquid E contains at least polishing abrasive grains and an electrolyte for maintaining an electrostatically charged state of the polishing abrasive grains. Since the electropolishing liquid having a high electric conductivity is used, it is possible to obtain a high electrolyzing current and to enlarge the distance between electrodes.

Abstract: A polishing method and a polishing apparatus by which excess portions of a metallic film 18 can be removed easily and efficiently in planarizing the metallic film 18 by polishing and which is high in accuracy of polishing, are provided. Also, a method of manufacturing a semiconductor device by use of the polishing method and the polishing apparatus is provided. A substrate 17 provided with the metallic film 18 and a counter electrode 15 are disposed oppositely to each other in an electrolytic solution E, an electric current is passed to the metallic film 18 through the electrolytic solution E, and the surface of the metallic film 18 is polished with a hard pad 14.

Abstract: The present invention is a method of producing semiconductor devices and an etching liquid with which the titanium nitride film can be removed without thinning of the CoSi layer. A hydrogen peroxide-water mixture is used for removal of the titanium nitride film in the method of producing semiconductor devices by cobalt salicide technology with titanium nitride as the cap film.

Abstract: A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film containing hafnium and silicon.

Abstract: A magnetic memory apparatus including a memory cell region and a peripheral circuitry region mounted on a substrate is provided. The memory cell region includes first wiring, second wiring that three-dimensionally intersects with the first wiring, and a magnetoresistance effect type memory device disposed in an intersecting region of the first and the second wiring for storing and reproducing information of a magnetic spin. The peripheral circuitry region includes first wiring that is in the same wiring layer as that of the first wiring in the memory cell region, and second wiring that is in the same wiring layer as the second wiring in the memory cell, and a magnetic material layer including a high magnetic permeability layer is formed on both side surfaces of the first wiring only within the memory cell region and on a surface opposite to a surface facing the memory device.

Abstract: An etching solution includes an anticorrosive for copper or a benzotriazole based anticorrosive in a hydrofluoric acid aqueous solution. An etching method makes use of the etching solution set out above. Moreover, a method for manufacturing a semiconductor device which should include the step of removing copper by the etching method. The method includes the steps of forming copper through a barrier layer made of a metal or metal compound, which is greater in ionization tendency than copper, so as to bury a wiring groove formed in an insulating film with the copper, followed by polishing additional copper and barrier layer formed on the insulating film, and etching a surface layer of the insulating film by use of the etching solution to remove an insulating defective layer made mainly of the barrier layer on the insulating film along with the surface layer of the insulating film.

Abstract: A polishing method and a polishing apparatus by which excess portions of a metallic film 18 can be removed easily and efficiently in planarizing the metallic film 18 by polishing and which is high in accuracy of polishing, are provided. Also, a method of manufacturing a semiconductor device by use of the polishing method and the polishing apparatus is provided. A substrate 17 provided with the metallic film 18 and a counter electrode 15 are disposed oppositely to each other in an electrolytic solution E, an electric current is passed to the metallic film 18 through the electrolytic solution E, and the surface of the metallic film 18 is polished with a hard pad 14.

Abstract: A polishing apparatus and a polishing method by which it is possible to restrain variations in the composition of an electrolytic solution 2 between a wafer 3 and a counter electrode 5, and the like, and to make current density distribution substantially constant in the plane of the wafer. The polishing apparatus, for planarizing a surface to be polished 3a by electrolytic combined polishing composed of a combination of electropolishing and mechanical polishing, includes a voltage impressing means 5 disposed oppositely to the surface to be polished 3a, and a discharging means for discharging foreign matter intermediately present between the voltage impressing means 5 and the object of polishing.

Abstract: The object is to make it possible to pass an electric current to the object of polishing with a stable current density distribution up to the end point of polishing, to use the same plating apparatus, cleaning apparatus and other apparatuses as those conventionally used, and to carry out the conventional manufacturing process flow. A substrate (1) provided with a metallic film (2) and a opposite electrode (3) are disposed oppositely to each other with a predetermined distance therebetween in an electrolytic solution, and an electric current is passed to the metallic film (2) through the electrolytic solution by an anode (4) set out of contact with the metallic film (2), so as to electropolish the metallic film (2). Simultaneously with the electropolishing, wiping is conducted by sliding a pad on the metallic film.

Abstract: An etching solution includes an anticorrosive for copper or a benzotriazole based anticorrosive in a hydrofluoric acid aqueous solution. An etching method makes use of the etching solution set out above. Moreover, a method for manufacturing a semiconductor device which should include the step of removing copper by the etching method. The method includes the steps of forming copper through a barrier layer made of a metal or metal compound, which is greater in ionization tendency than copper, so as to bury a wiring groove formed in an insulating film with the copper, followed by polishing additional copper and barrier layer formed on the insulating film, and etching a surface layer of the insulating film by use of the etching solution to remove an insulating defective layer made mainly of the barrier layer on the insulating film along with the surface layer of the insulating film.

Abstract: A magnetic memory apparatus including a memory cell region and a peripheral circuitry region mounted on a substrate is provided. The memory cell region includes first wiring, second wiring that three-dimensionally intersects with the first wiring, and a magnetoresistance effect type memory device disposed in an intersecting region of the first and the second wiring for storing and reproducing information of a magnetic spin. The peripheral circuitry region includes first wiring that is in the same wiring layer as that of the first wiring in the memory cell region, and second wiring that is in the same wiring layer as the second wiring in the memory cell, and a magnetic material layer including a high magnetic permeability layer is formed on both side surfaces of the first wiring only within the memory cell region and on a surface opposite to a surface facing the memory device.

Abstract: There are provided a polishing method and a polishing apparatus for appropriately controlling the potential of an acting electrode to perform an accurate and stable electrolytic polishing process. There is also provided a method of manufacturing a semiconductor device using the polishing method and the polishing apparatus. In the polishing method according to the present invention, a substrate with a metal film formed thereon and a counter electrode are disposed in facing relation to each other in an electrolytic liquid, and a current is supplied to the metal film through the electrolytic liquid based on the potential of the metal film with respect to a reference electrode.

Abstract: Electric conductivity is enhanced without causing coagulation or precipitation of polishing abrasive grains. In addition, good planarization is realized without inducing defects in a metallic film or a wiring which are to be polished.