Patents by Inventor Kaori Takimoto

Kaori Takimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145496
    Abstract: Imaging devices and ranging devices are disclosed. In one example, an imaging device includes a semiconductor substrate, a first pixel array, a second pixel array, and a control unit. In the first pixel array, a first light receiving pixel on the semiconductor substrate has a stacked structure of a first electrode, a photoelectric conversion layer, and a second electrode (80). It photoelectrically converts light in a first wavelength region including the visible light region. In the second pixel array, a second light receiving pixel is provided at a position overlapping the first light receiving pixel in a thickness direction of the semiconductor substrate. It photoelectrically converts light in a second wavelength region including the infrared light region. The control unit drives and controls the second pixel array based on a signal photoelectrically converted by the first pixel array.
    Type: Application
    Filed: February 22, 2022
    Publication date: May 2, 2024
    Inventors: Hideaki Togashi, Kaori Takimoto, Masahiro Segami, Kei Nakagawa, Nobuhiro Kawai
  • Publication number: 20230034528
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 11489015
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Publication number: 20220310680
    Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Taizo TAKACHI, Yuichi YAMAMOTO, Suguru SAITO, Satoru WAKIYAMA, Yoichi OOTSUKA, Naoki KOMAI, Kaori TAKIMOTO, Tadashi IIJIMA, Masaki HANEDA, Masaya NAGATA
  • Patent number: 11454746
    Abstract: To make it possible to restrain generation of chipping or cracking in a substrate of a laminated lens structure. A laminated lens structure includes substrates with lens which each have a lens disposed inside a through-hole formed in the substrate and which are laminated on one another by direct bonding, in which the substrates are each provided in the vicinity of the outer circumference thereof with through grooves penetrating the substrate. The present technology is applicable, for example, to a compound eye camera module.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 27, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Atsushi Yamamoto, Kaori Takimoto
  • Patent number: 11282911
    Abstract: Display devices, display modules, and methods of manufacture are disclosed. In one example, a display device includes a pixel region in which pixels for displaying an image are arranged, on an upper surface of a substrate. A device-side signal electrode for exchanging a signal related to the pixels with an outside is disposed on a side surface of the substrate. A module casing is configured to store the display device and to have a casing-side signal electrode electrically connected to the device-side signal electrode in a spot facing the device-side signal electrode.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: March 22, 2022
    Assignee: Sony Group Corporation
    Inventors: Hiroshi Horikoshi, Masato Kawashima, Kaori Takimoto, Masaya Nagata
  • Publication number: 20210028234
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 10840303
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masahiro Joei, Kaori Takimoto
  • Publication number: 20200357838
    Abstract: Provided is a laminated lens structure capable of corresponding various optical parameters. The laminated lens structure includes at least one or more sheets of first lens-attached substrates and at least one or more sheets of second lens-attached substrates as a lens-attached substrate including a lens resin portion that forms a lens, and a carrier substrate that carries the lens resin portion. The carrier substrate of the first lens-attached substrates is constituted by laminating a plurality of sheets of carrier configuration substrates in a thickness direction, and the carrier substrate of the second lens-attached substrates is constituted by one sheet of carrier configuration substrate. For example, the present technology is applicable to a camera module and the like.
    Type: Application
    Filed: August 17, 2018
    Publication date: November 12, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Munekatsu FUKUYAMA, Hirotaka YOSHIOKA, Kunihiko HIKICHI, Atsushi YAMAMOTO, Kaori TAKIMOTO, Minoru ISHIDA
  • Patent number: 10804312
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit 5 of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive 10 material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Publication number: 20200258924
    Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
    Type: Application
    Filed: October 16, 2018
    Publication date: August 13, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Taizo TAKACHI, Yuichi YAMAMOTO, Suguru SAITO, Satoru WAKIYAMA, Yoichi OOTSUKA, Naoki KOMAI, Kaori TAKIMOTO, Tadashi IIJIMA, Masaki HANEDA, Masaya NAGATA
  • Publication number: 20190369299
    Abstract: To make it possible to restrain generation of chipping or cracking in a substrate of a laminated lens structure. A laminated lens structure includes substrates with lens which each have a lens disposed inside a through-hole formed in the substrate and which are laminated on one another by direct bonding, in which the substrates are each provided in the vicinity of the outer circumference thereof with through grooves penetrating the substrate. The present technology is applicable, for example, to a compound eye camera module.
    Type: Application
    Filed: January 16, 2018
    Publication date: December 5, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsushi YAMAMOTO, Kaori TAKIMOTO
  • Publication number: 20190341417
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Applicant: Sony Corporation
    Inventors: Masaya NAGATA, Kaori TAKIMOTO
  • Patent number: 10403669
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Publication number: 20190237513
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 10304904
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masahiro Joei, Kaori Takimoto
  • Publication number: 20190115414
    Abstract: [Object] To enable further reducing a chip area. [Solution] Provided is a display module including: a display device configured such that a pixel region in which a plurality of pixels for displaying an image are arranged is formed on an upper surface of a substrate, and a device-side signal electrode for exchanging a signal related to the pixels with an outside is disposed on a side surface of the substrate; and a module casing configured to store the display device and have a casing-side signal electrode electrically connected to the device-side signal electrode in a spot facing the device-side signal electrode.
    Type: Application
    Filed: April 14, 2017
    Publication date: April 18, 2019
    Inventors: Hiroshi Horikoshi, Masato Kawashima, Kaori Takimoto, Masaya Nagata
  • Publication number: 20180301510
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Application
    Filed: June 26, 2018
    Publication date: October 18, 2018
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 10014349
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 3, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masahiro Joei, Kaori Takimoto
  • Publication number: 20180166491
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Application
    Filed: June 2, 2016
    Publication date: June 14, 2018
    Inventors: Masaya NAGATA, Kaori TAKIMOTO