Abstract: According to one embodiment, a semiconductor memory device includes a MOS transistor and a drive circuit. The MOS transistor has a gate and a gate insulating film. The drive circuit is coupled to the gate and supplies a first voltage that destroys the gate insulating film or a second voltage lower than the first voltage. The drive circuit applies the first voltage to the gate in a first write to the MOS transistor, and applies the second voltage to the gate in a second write to the MOS transistor.

Abstract: In a semiconductor memory device of an embodiment, a write circuit includes an inversion circuit configured to invert write data and output the inverted write data, a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array, a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array, and a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data.

Abstract: In a semiconductor memory device of an embodiment, a write circuit includes an inversion circuit configured to invert write data and output the inverted write data, a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array, a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array, and a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data.

Abstract: According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the test data storing memory cells when testing the bit line and makes data to be read out from the read data storing memory cells when reading out the read data.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions provided on a substrate and electrically separated from each other, a memory cell block provided in each of the semiconductor regions and includes nonvolatile memory cells, word lines connected to control gates of memory transistors so as to commonly connect memory transistors in a same row, select gate lines connected to gates of select transistors so as to commonly connect select transistors in a same row, and a row decoder configured to apply a first negative voltage to a selected word line from which data is erased, and to apply a second positive voltage to a non-selected word lines from which data is not erased while an erasing voltage is applied to the semiconductor region upon erasing operation.

Abstract: According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the test data storing memory cells when testing the bit line and makes data to be read out from the read data storing memory cells when reading out the read data.

Abstract: A photo-mask that includes a first light shielding region which is narrow and elongated, and a second light shielding region which is wider and more elongated than the first light shielding region and is away from the first light shielding region. A phase shifter part and a non-phase shifter part are provided adjacently to both sides of the first light shielding region. Two phase shifter parts or two non-phase shifter parts are respectively provided adjacently to both sides of the second light shielding part.

Abstract: A photo-mask, a multiphase exposure method and a method of manufacturing a semiconductor device are disclosed. The photo-mask mask includes a first light shielding region which is narrow and elongated, and a second light shielding region which is wider and more elongated than the first light shielding region and is away from the first light shielding region. A phase shifter part and a non-phase shifter part are provided adjacently to both sides of the first light shielding region. Two phase shifter parts or two non-phase shifter parts are respectively provided adjacently to both sides of the second light shielding part.

Abstract: A semi conductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Abstract: A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Abstract: A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value.

Abstract: A memory cell of a static semiconductor memory device includes first and second inverters, first and second variable resistors and first and second transfer transistors. The first variable resistor is connected between an output terminal of the first inverter and an input terminal of the second inverter. The second variable resistor is connected between an output terminal of the second inverter and an input terminal of the first inverter. The first transfer transistor has a current path connected between the output terminal of the first inverter and a first bit line and a gate connected to a word line. The second transfer transistor has a current path connected between the output terminal of the second inverter and a second bit line and a gate connected to the word line.

Abstract: According to this invention, an oxide film is formed on a semiconductor substrate, a metallic boron film or a film containing at least one selected from the group consisting of boron, phosphorus, and arsenic is deposited on the surface of the resultant structure. At least one selected from the group consisting of boron, phosphorus, and arsenic is doped from the metallic boron film or the film containing at least one selected from the group consisting of boron, phosphorus, and arsenic to the oxide film by diffusion without diffusing into the semiconductor substrate. Thus, a semiconductor device having good radiation resistance can be obtained.