Patents by Inventor Kaoru Katoh

Kaoru Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9018281
    Abstract: Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ?100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ?20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg?30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg?30)° C. is ?42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 28, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Kazuaki Sumita, Kaoru Katoh, Taro Shimoda
  • Publication number: 20140334214
    Abstract: In a switching circuit in which a power semiconductor switching element and a unipolar type diode are connected in parallel, the noise due to ringing is reduced. When the main circuit current flowing is equal to or less than a predetermined value, an Si-IGBT is switched and driven by a gate resistance. In this case, when the main circuit current detected is equal to or more than a threshold value, a main circuit current detection circuit changes a gate resistance switching pMOS from ON state to OFF state. Accordingly, the Si-IGBT operates with a summation of a gate resistance and a gate resistor. More specifically, a gate resistance value of a gate drive circuit of the Si-IGBT increases. Therefore, dv/dt of the collector-emitter voltage of the Si-IGBT, i.e., the recovery dv/dt of the unipolar type diode, is small, and therefore, the noise due to ringing can be reduced.
    Type: Application
    Filed: October 12, 2012
    Publication date: November 13, 2014
    Inventors: Kaoru Katoh, Katsumi Ishikawa, Kazutoshi Ogawa
  • Patent number: 8330524
    Abstract: A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
  • Publication number: 20120229192
    Abstract: A semiconductor integrated circuit which reduces an increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 13, 2012
    Inventors: Kaoru KATOH, Shigeki KOYA, Shinichiro TAKATANI, Yasushi SHIGENO, Akishige NAKAJIMA, Takashi OGAWA
  • Patent number: 8163556
    Abstract: The invention provides a substrate suitable for cell culture observation and a method of observation using the same. Crystalline carbon such as a graphite powder is mixed into a thermosetting resin such as a furan resin, and the mixture is molded in the shape of a sheet and carbonized to produce a carbon substrate; then, a cell is made to adhere to the carbon substrate, and the cell is caused to proliferate on the carbon substrate and observed using a microscope.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: April 24, 2012
    Assignees: Mitsubishi Pencil Co., Ltd., Kaora Katoh, Hiroko Kaneko
    Inventors: Yoshihisa Suda, Kunitaka Yamada, Hiroko Kaneko, Kaoru Katoh, Harumasa Okamoto
  • Patent number: 8159282
    Abstract: The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF Tx signal to a bias generation circuit of an antenna switch. A semiconductor integrated circuit includes an antenna switch having a bias generation circuit, a Tx switch, and an antenna switch having a bias generation circuit, a transmitter switch, and a receiver (Rx) switch. The on/off state of a transistor of a Tx switch coupled between a Tx port and an I/O port is controlled by a Tx control bias. The on/off state of the transistors of the Rx switch coupled between the I/O port and a receiver (Rx) port is controlled by an RX control bias. A radio frequency (RF) signal input port of the bias generation circuit is coupled to the Tx port, and a negative DC output bias generated from a DC output port can be supplied to a gate control port of transistors of the Rx switch.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
  • Publication number: 20120074596
    Abstract: Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ?100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ?20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg?30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg?30)° C. is ?42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.
    Type: Application
    Filed: November 4, 2011
    Publication date: March 29, 2012
    Inventors: Kazuaki Sumita, Kaoru Katoh, Taro Shimoda
  • Publication number: 20110221519
    Abstract: The present invention reduces harmonic components of an RF transmission output signal. In the semiconductor integrated circuit which the present invention provides, a transmission switch of an antenna switch thereof includes transmission field effect transistors whose S-D current paths are coupled between a transmission terminal and an input/output terminal and whose gate terminals are coupled to a transmission control terminal. A reception switch of the antenna switch includes reception field effect transistors whose S-D current paths are coupled between the input/output terminal and a reception terminal and whose gate terminals are coupled to a reception control terminal. The transmission and reception n-channel MOS field effect transistors are respectively formed in a silicon-on-insulator structure.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 15, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kaoru KATOH, Shigeki KOYA, Yasushi SHIGENO, Akishige NAKAJIMA, Takashi OGAWA
  • Patent number: 7829381
    Abstract: A method of manufacturing a semiconductor device comprising the steps of (1) applying an underfill composition to a surface of a silicon wafer, (2) dicing the silicon wafer into chips, (3) positioning the chip, and (4) bonding the chip to the substrate, characterized in that the underfill composition consists of a first underfill composition and a second underfill composition, the step (1) comprises the steps of (i) applying the first underfill composition on the surface of the silicon wafer and then bringing the applied first underfill composition into a B-stage to form a layer of the first underfill composition having a thickness ranging from 0.5 to 1.0 time the height of the solder bump, and (ii) applying the second underfill composition on the B-stage first underfill composition layer and bringing the applied second underfill composition into a B-stage to form a layer wherein a total thickness of the B-stage first underfill composition and the B-stage second underfill composition ranges from 1.0 to 1.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: November 9, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Kaoru Katoh
  • Publication number: 20100117713
    Abstract: The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF Tx signal to a bias generation circuit of an antenna switch. A semiconductor integrated circuit includes an antenna switch having a bias generation circuit, a Tx switch, and an antenna switch having a bias generation circuit, a transmitter switch, and a receiver (Rx) switch. The on/off state of a transistor of a Tx switch coupled between a Tx port and an I/O port is controlled by a Tx control bias. The on/off state of the transistors of the Rx switch coupled between the I/O port and a receiver (Rx) port is controlled by an RX control bias. A radio frequency (RF) signal input port of the bias generation circuit is coupled to the Tx port, and a negative DC output bias generated from a DC output port can be supplied to a gate control port of transistors of the Rx switch.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 13, 2010
    Inventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
  • Publication number: 20100016474
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) an amine curing agent, and (C) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A), wherein the component (B) is contained in such an amount that a molar ratio of epoxy groups of the component (A) to amino groups of the component (B), ranges from 0.6 to less than 1.0, provided that, if the component (B) includes an amine curing agent which is solid in the composition at a temperature of from room temperature to 150° C., a content of such an amine is 30 mol % or less, based on the component (B).
    Type: Application
    Filed: July 8, 2009
    Publication date: January 21, 2010
    Inventors: Masatoshi ASANO, Kaoru Katoh, Kazuaki Sumita
  • Publication number: 20100001415
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin; (B) an amine curing agent; (C) a nitrogen compound selected from the group consisting of organic acids salts of tertiary amines, amino acids, imino acids, and monoamine compounds having an alcoholic hydroxyl group in an amount of from 0.1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Application
    Filed: July 31, 2009
    Publication date: January 7, 2010
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Patent number: 7642661
    Abstract: A liquid epoxy resin composition comprising: (A) a liquid epoxy resin; (B) an amine type curing agent; (C) a sulfur-containing phenol compound in an amount of from 1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: January 5, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Publication number: 20090142884
    Abstract: A method of manufacturing a semiconductor device comprising the steps of (1) applying an underfill composition to a surface of a silicon wafer, (2) dicing the silicon wafer into chips, (3) positioning the chip, and (4) bonding the chip to the substrate, characterized in that the underfill composition consists of a first underfill composition and a second underfill composition, the step (1) comprises the steps of (i) applying the first underfill composition on the surface of the silicon wafer and then bringing the applied first underfill composition into a B-stage to form a layer of the first underfill composition having a thickness ranging from 0.5 to 1.0 time the height of the solder bump, and (ii) applying the second underfill composition on the B-stage first underfill composition layer and bringing the applied second underfill composition into a B-stage to form a layer wherein a total thickness of the B-stage first underfill composition and the B-stage second underfill composition ranges from 1.0 to 1.
    Type: Application
    Filed: November 25, 2008
    Publication date: June 4, 2009
    Inventor: Kaoru KATOH
  • Publication number: 20080070054
    Abstract: A set of compositions for preparing a system-in-package type semiconductor device, characterized in that the set of compositions consists of an underfill composition for preparing the underfill part and an encapsulation resin composition for preparing the resin encapsulation part, wherein 1) a cured product of the underfill composition has a glass transition temperature, Tg, which is 100° C. or higher and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by 20° C. or smaller, 2) a total of a linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg-30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg-30)° C. is 42 ppm/° C.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 20, 2008
    Inventors: Kazuaki Sumita, Kaoru Katoh, Taro Shimoda
  • Publication number: 20070134844
    Abstract: The invention relates to a process for producing a semiconductor device in which a circuit substrate and a semiconductor chip are connected through a plurality of solder bump electrodes, said process comprising applying a non-cleaning type flux to at least a portion of a bonding pad in the circuit substrate and a semiconductor chip; applying an under-fill material to the circuit substrate or the semiconductor chip; positioning the semiconductor chip and the circuit substrate; and bonding the semiconductor chip and the circuit substrate through a thermocompression bonding, and a semiconductor device produced by the process. By using the process, since it is not necessary to add a flux component deteriorating the reliability of an under-fill material as the sealant to the under-fill material, reliability of the semiconductor device is not deteriorated. Further, since the intrusion step of thin film is not used, mounting can be conducted in a relatively short time.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 14, 2007
    Inventors: Kaoru Katoh, Masatoshi Asano, Hiroyuki Takenaka, Kazuaki Sumita
  • Publication number: 20070116962
    Abstract: A liquid epoxy resin composition comprising: (A) a liquid epoxy resin; (B) an amine type curing agent; (C) a sulfur-containing phenol compound in an amount of from 1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Application
    Filed: November 20, 2006
    Publication date: May 24, 2007
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Publication number: 20070104960
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin (B) an amine curing agent and (C) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A), wherein the component (B) is contained in such an amount that a molar ratio of epoxy groups of the component (A) to amino groups of the component (B), ranges from 0.6 to less than 1.0, provided that, if the component (B) includes an amine curing agent which is solid in the composition at a temperature of from room temperature to 150° C., a content of such an amine is 30 mol % or less, based on the component (B).
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Publication number: 20070104959
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin (B) an amine curing agent (C) a nitrogen compound selected from the group consisting of organic acids salts of tertiary amines, amino acids, imino acids, and monoamine compounds having an alcoholic hydroxyl group in an amount of from 0.1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B), and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Application
    Filed: November 1, 2006
    Publication date: May 10, 2007
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Patent number: 7169833
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) an aromatic amine curing agent comprising 5–100% by weight of a specific aromatic amine compound having a purity of at least 99%, (C) an inorganic filler, and (D) an ester organic solvent having a boiling point of 130–250° C. is useful for semiconductor encapsulation. The composition has an infiltration ability, adhesion to silicon chips, resistance to deterioration under hot humid conditions, and resistance to thermal shocks.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: January 30, 2007
    Assignee: Shin-Estu Chemical Co., Ltd.
    Inventors: Kazuaki Sumita, Kaoru Katoh, Tokue Kojima, Toshio Shiobara