Patents by Inventor Kaoru Kawai

Kaoru Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6960494
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Publication number: 20050051810
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Application
    Filed: October 21, 2004
    Publication date: March 10, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Patent number: 6836012
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: December 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Publication number: 20030183946
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first semiconductor chip having a thickness of 0.25 mm or less and mounted on the substrate through flip-chip connection with a gap of 0.055 mm or less, a conductive connector member connecting the chip to the substrate, and a molding resin layer covering the chip and formed of a cured resin comprising 75-92% by weight of an inorganic filler and 0.5-1.5% by weight of carbon black, a portion of the molding resin layer opposite to the substrate having a thickness of 0.15 mm or less, 99 wt % of the filler having longest diameter of 35 &mgr;m or less, the average longest diameter of the filler being 15 &mgr;m or less, and the content of fine filler having a longest diameter of 10 &mgr;m or less is within the range of 30-50% by weight based on the entire filler.
    Type: Application
    Filed: March 27, 2003
    Publication date: October 2, 2003
    Inventors: Masatoshi Fukuda, Kaoru Kawai
  • Publication number: 20020140095
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata