Patents by Inventor Kaoru Koyanagi

Kaoru Koyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9018795
    Abstract: The objective of this invention is to provide an autonomous distributed electric power system without depending on a known electric power system. In order to achieve such objective, this invention proposes a following feature: Output frequencies of autonomous grid-connection inverters (104, 164) are to be variably controlled by the control system depending on a change of a stored electric power amount [kWh] of the direct current electric power storage device (102) within an alternating-current autonomous-distributed electric power system; and, such electric power system is built of plural electric power supplier and demander (11, 12, 13, 14, 15) who have electric power storage devices with a system which can control such inverters (104, 164); those inverters are voltage self-exciting as well.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 28, 2015
    Assignee: VPEC, Inc.
    Inventors: Kaoru Koyanagi, Satoshi Nagata
  • Publication number: 20110175443
    Abstract: The objective of this invention is to provide an autonomous distributed electric power system without depending on a known electric power system. In order to achieve such objective, this invention proposes a following feature: Output frequencies of autonomous grid-connection inverters (104, 164) are to be variably controlled by the control system depending on a change of a stored electric power amount [kWh] of the direct current electric power storage device (102) within an alternating-current autonomous-distributed electric power system; and, such electric power system is built of plural electric power supplier and demander (11, 12, 13, 14, 15) who have electric power storage devices with a system which can control such inverters (104, 164); those inverters are voltage self-exciting as well.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 21, 2011
    Applicant: VPEC, INC.
    Inventors: Kaoru Koyanagi, Satoshi Nagata
  • Patent number: 7761402
    Abstract: This invention relates to a method of determining stability of unstable equilibrium point (UEP) computed by using BCU method, comprising selecting UEP computed by using BCU method, obtaining a test vector Xtest for the selected UEP, say XUEP using the following equation: Xtest=Xspost+0.99(XUEP?Xspost) where Xspost is the SEP, and checking boundary condition of XUEP by simulating system trajectory of post-fault original system starting from Xtest.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: July 20, 2010
    Assignees: The Tokyo Electric Power Company, Incorporated, Bigwood Systems, Incorporated
    Inventors: Hsiao-Dong Chiang, Hua Li, Yasuyuki Tada, Tsuyoshi Takazawa, Takeshi Yamada, Atsushi Kurita, Kaoru Koyanagi
  • Patent number: 7483826
    Abstract: This invention relates to a method of determining stability of unstable equilibrium point (UEP) computed by using BCU method, comprising selecting UEP computed by using BCU method, obtaining a test vector Xtest for the selected UEP, say XUEP using the following equation: Xtest=Xspost+0.99(XUEP?Xspost) where Xspost is the SEP, and checking boundary condition of XUEP by simulating system trajectory of post-fault original system starting from Xtest.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: January 27, 2009
    Assignees: The Tokyo Electric Power Company, Incorporated, Bigwood Systems, Incorporated
    Inventors: Hsiao-Dong Chiang, Hua Li, Yasuyuki Tada, Tsuyoshi Takazawa, Takeshi Yamada, Atsushi Kurita, Kaoru Koyanagi
  • Publication number: 20080126060
    Abstract: This invention relates to a method of determining stability of unstable equilibrium point (UEP) computed by using BCU method, comprising selecting UEP computed by using BCU method, obtaining a test vector Xtest for the selected UEP, say XUEP using the following equation: Xtest=Xspost+0.99(XUEP?Xspost) where Xspost is the SEP, and checking boundary condition of XUEP by simulating system trajectory of post-fault original system starting from Xtest.
    Type: Application
    Filed: February 1, 2008
    Publication date: May 29, 2008
    Applicant: The Tokyo Electric Power Co. Inc.
    Inventors: Hsiao-Dong CHIANG, Hua Li, Yasuyuki Tada, Tsuyoshi Takazawa, Takeshi Yamada, Atsushi Kurita, Kaoru Koyanagi
  • Publication number: 20060190227
    Abstract: This invention relates to a method of determining stability of unstable equilibrium point (UEP) computed by using BCU method, comprising selecting UEP computed by using BCU method, obtaining a test vector Xtest for the selected UEP, say XUEP using the following equation: Xtest=Xspost+0.99(XUEP?Xspost) where Xspost is the SEP, and checking boundary condition of XUEP by simulating system trajectory of post-fault original system starting from Xtest.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 24, 2006
    Applicants: The Tokyo Electric Power Co. Inc., Bigwood Systems, Incorporated
    Inventors: Hsiao-Dong Chiang, Hua Li, Yasuyuki Tada, Tsuyoshi Takazawa, Takeshi Yamada, Atsushi Kurita, Kaoru Koyanagi
  • Patent number: 6868311
    Abstract: A system for on-line dynamic screening of contingencies comprising postulated disturbances which an electric power system may experience, the system comprising a dynamic contingency screening program for evaluating a plurality of contingencies with a plurality of contingency classifiers based on the method of finding the controlling unstable equilibrium point of the power system known as the boundary of stability region based controlling unstable equilibrium point method by sequentially applying the contingencies to a network islanding problem classifier, S.E.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 15, 2005
    Assignees: The Tokyo Electric Power Company, Incorporated
    Inventors: Hsiao-Dong Chiang, Atsushi Kurita, Hiroshi Okamoto, Ryuya Tanabe, Yasuyuki Tada, Kaoru Koyanagi, Yicheng Zhou
  • Publication number: 20030200010
    Abstract: A system for on-line dynamic screening of contingencies comprising postulated disturbances which an electric power system may experience, the system comprising a dynamic contingency screening program for evaluating a plurality of contingencies with a plurality of contingency classifiers based on the method of finding the controlling unstable equilibrium point of the power system known as the boundary of stability region based controlling unstable equilibrium point method by sequentially applying the contingencies to a network islanding problem classifier, S.E.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 23, 2003
    Inventors: Hsiao-Dong Chiang, Atsushi Kurita, Hiroshi Okamoto, Ryuya Tanabe, Yasuyuki Tada, Kaoru Koyanagi, Yicheng Zhou
  • Patent number: 5353140
    Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: October 4, 1994
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
  • Patent number: 5296405
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: March 22, 1994
    Assignee: Semiconductor Energy Laboratory Co.., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5196954
    Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: March 23, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
  • Patent number: 5171710
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: December 15, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5089426
    Abstract: An improved semiconductor device is disclosed which is free from current leakage due to pin-holes or other gaps. Also an improved method for provessing a semiconductor device is shown. According to the invention, gaps produced in fabricating process of the semiconductor layer are filled with insulator in advance of deposition of electrodes. By virtue of this configuration, short current paths do not result even if transparent electrode is provided on the semiconductor layer.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: February 18, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Masato Susukida, Mikio Kinka, Takeshi Fukada, Masayoshi Abe, Ippei Kobayashi, Katsuhiko Shibata, Kaoru Koyanagi, Susumu Nagayama
  • Patent number: 4986213
    Abstract: An improved semiconductor processing is desclosed. In the manufacturing process, just formed semiconductor layer undergoes photo annealing and latent dangling bonds are let appear on the surface and gaps, then neutralizer is introduced to the ambience of the semiconductor. The semiconductor thus formed demonstrates SEL effect in place of Staebler-Wronski effect.
    Type: Grant
    Filed: September 28, 1988
    Date of Patent: January 22, 1991
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 4937651
    Abstract: An improved semiconductor device is disclosed which is free from current leakage due to pin-holes or other gaps. Also an improved method for processing a semiconductor device is shown. According to the invention, gaps produced in fabricating process of the semiconductor layer are filled with insulator in advance of deposition of electrodes.
    Type: Grant
    Filed: August 22, 1986
    Date of Patent: June 26, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Mikio Kinka, Takeshi Fukada, Masayoshi Abe, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Susumu Nagayama, Kaoru Koyanagi
  • Patent number: 4888305
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, just formed semiconductor layer undergoes photo annealing and latent dangling bonds are let appear on the surface and gaps, then neutralizer is introduced to the ambience of the semiconductor. The semiconductor thus formed demonstrates SEL effect in place of Staebler-Wronski effect.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: December 19, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 4861143
    Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.
    Type: Grant
    Filed: December 2, 1987
    Date of Patent: August 29, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
  • Patent number: 4812415
    Abstract: An improved semiconductor device is disclosed which is free from current leakage due to pin-holes or other gaps. Also an improved method for processing a semiconductor device is shown. According to the invention, gaps produced during the fabricating process of the semiconductor layer are filled with insulator in advance of deposition of electrodes. By virtue of this configuration, short current paths do not result when electrodes are provided on the semiconductor layer.
    Type: Grant
    Filed: August 6, 1987
    Date of Patent: March 14, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Mikio Kinka, Takeshi Fukada, Masayoshi Abe, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Susumu Nagayama, Kaoru Koyanagi
  • Patent number: 4799776
    Abstract: The liquid crystal display according to this invention comprises a liquid crystal cell having a pair of substrates with faced insides which are provided with electrodes, ferroelectric liquid crystal with a chiral smectic C phase in between said substrates and a polarizing plate on the light incidence side. One of said electrodes is a relfective electrode. The display is utilized with microcomputers, word processors, television or so on, and wherein, due to a small number of parts, the absorption loss of light is small and a reflective plate is prevented from being oxided and therefore degraded in reflection index, since it is not exposed to air.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: January 24, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Inujima, Akira Mase, Toshimitsu Konuma, Mitsunori Sakama, Toshiji Hamatani, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
  • Patent number: 4786607
    Abstract: An improved semiconductor device is disclosed which is free from current leakage due to pin-holes or other gaps. Also an improved method for processsing a semiconductor device is shown. According to the invention, gaps produced in fabricating process of the semiconductor layer are filled with insulator in advance of deposition of electrodes.
    Type: Grant
    Filed: September 4, 1987
    Date of Patent: November 22, 1988
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shumpei Yamazaki, Kunio Suzuki, Mikio Kinka, Takeshi Fukada, Masayoshi Abe, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Susumu Nagayama, Kaoru Koyanagi