Patents by Inventor Kaoru Mikagi
Kaoru Mikagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7793818Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: GrantFiled: September 23, 2009Date of Patent: September 14, 2010Assignee: NEC CorporationInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Publication number: 20100015796Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: ApplicationFiled: September 23, 2009Publication date: January 21, 2010Applicant: NEC CorporationInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 7611041Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: GrantFiled: August 30, 2007Date of Patent: November 3, 2009Assignee: NEC CorporationInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 7560372Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.Type: GrantFiled: September 25, 2006Date of Patent: July 14, 2009Assignee: NEC Electronics CorporationInventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
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Publication number: 20070295786Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: ApplicationFiled: August 30, 2007Publication date: December 27, 2007Applicant: NEC CORPORATIONInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 7282432Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: GrantFiled: June 6, 2005Date of Patent: October 16, 2007Assignee: NEC CorporationInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 7170172Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.Type: GrantFiled: December 13, 2002Date of Patent: January 30, 2007Assignee: NEC Electronics CorporationInventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
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Publication number: 20070015351Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.Type: ApplicationFiled: September 25, 2006Publication date: January 18, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
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Patent number: 6989328Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mAĆsec/cm2.Type: GrantFiled: February 13, 2004Date of Patent: January 24, 2006Assignee: NEC Electronics CorporationInventors: Koji Arita, Kaoru Mikagi, Ryohei Kitao
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Publication number: 20050279812Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: ApplicationFiled: June 6, 2005Publication date: December 22, 2005Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 6969915Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: GrantFiled: January 14, 2002Date of Patent: November 29, 2005Assignee: NEC CorporationInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Publication number: 20040161928Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.Type: ApplicationFiled: February 13, 2004Publication date: August 19, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Koji Arita, Kaoru Mikagi, Ryohei Kitao
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Publication number: 20030111731Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.Type: ApplicationFiled: December 13, 2002Publication date: June 19, 2003Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
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Patent number: 6569766Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.Type: GrantFiled: October 27, 2000Date of Patent: May 27, 2003Assignee: NEC Electronics CorporationInventors: Nobuaki Hamanaka, Ken Inoue, Kaoru Mikagi
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Patent number: 6566254Abstract: A silicide film is selectively formed at least on diffusion layers of a MOS transistor. In the method for forming the silicide film includes, a first metal film is selectively formed at least on diffusion layers. A first annealing is applied to allow at least the diffusion layers to react with the first metal film. A part of the sidewalls is removed to form a gap with reacted film of the first metal film. A second annealing is performed at a temperature higher than that of the first annealing to form a reacted film. This makes it possible to form a silicide film having preferable electric characteristics on a gate and diffusion layers being fine in dimension and high in impurity concentration, in a self-aligning fashion without producing “bite of silicide.Type: GrantFiled: January 21, 2000Date of Patent: May 20, 2003Assignee: NEC Electronics CorporationInventor: Kaoru Mikagi
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Publication number: 20030077901Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.Type: ApplicationFiled: April 28, 2000Publication date: April 24, 2003Inventors: NOBUAKI HAMANAKA, KEN INOUE, KAORU MIKAGI
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Patent number: 6548421Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.Type: GrantFiled: April 28, 2000Date of Patent: April 15, 2003Assignee: NEC CorporationInventors: Nobuaki Hamanaka, Ken Inoue, Kaoru Mikagi
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Publication number: 20030025202Abstract: An external electrode in a semiconductor device includes, from the bottom of a wafer, a wiring pad, first and second barrier metal layers, a solder-wetting film and a solder ball. The first barrier metal layer has a tensile internal stress and a granular crystalline structure, whereas the second barrier metal layer has a compressive internal stress and a pillar crystalline structure. The two-layer structure of the barrier metal film has an excellent barrier function against Sn diffusion from the solder ball and reduces the internal stress of the barrier metal film.Type: ApplicationFiled: July 17, 2002Publication date: February 6, 2003Applicant: NEC CorporationInventors: Kaoru Mikagi, Akira Furuya, Keisuke Hatano
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Publication number: 20020093096Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead flee solder is thinly formed on a UBM layer The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.Type: ApplicationFiled: January 14, 2002Publication date: July 18, 2002Applicant: NEC CORPORATIONInventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
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Patent number: 6413807Abstract: Silicide films having a high heat-resistance are formed on a gate electrode, simultaneously with silicide films having good junction leakage characteristics on diffusion layers. A transistor includes a polycrystalline silicon gate electrode, a gate insulating film, a diffusion layer, and sidewalls on a silicon substrate isolated by an element isolation oxide film. A first silicide film and a second silicide film are formed on the gate electrode and on the diffusion layer, respectively. The first silicide film is thicker than the second silicide film.Type: GrantFiled: June 2, 2000Date of Patent: July 2, 2002Assignee: NEC CorporationInventor: Kaoru Mikagi