Patents by Inventor Kaoru Mikagi

Kaoru Mikagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7793818
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: September 14, 2010
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Publication number: 20100015796
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 21, 2010
    Applicant: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 7611041
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: November 3, 2009
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 7560372
    Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 14, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
  • Publication number: 20070295786
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: August 30, 2007
    Publication date: December 27, 2007
    Applicant: NEC CORPORATION
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 7282432
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: October 16, 2007
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 7170172
    Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 30, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
  • Publication number: 20070015351
    Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.
    Type: Application
    Filed: September 25, 2006
    Publication date: January 18, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
  • Patent number: 6989328
    Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mAƗsec/cm2.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: January 24, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Koji Arita, Kaoru Mikagi, Ryohei Kitao
  • Publication number: 20050279812
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: June 6, 2005
    Publication date: December 22, 2005
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 6969915
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: November 29, 2005
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Publication number: 20040161928
    Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koji Arita, Kaoru Mikagi, Ryohei Kitao
  • Publication number: 20030111731
    Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 19, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
  • Patent number: 6569766
    Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 27, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Nobuaki Hamanaka, Ken Inoue, Kaoru Mikagi
  • Patent number: 6566254
    Abstract: A silicide film is selectively formed at least on diffusion layers of a MOS transistor. In the method for forming the silicide film includes, a first metal film is selectively formed at least on diffusion layers. A first annealing is applied to allow at least the diffusion layers to react with the first metal film. A part of the sidewalls is removed to form a gap with reacted film of the first metal film. A second annealing is performed at a temperature higher than that of the first annealing to form a reacted film. This makes it possible to form a silicide film having preferable electric characteristics on a gate and diffusion layers being fine in dimension and high in impurity concentration, in a self-aligning fashion without producing “bite of silicide.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: May 20, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Kaoru Mikagi
  • Publication number: 20030077901
    Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.
    Type: Application
    Filed: April 28, 2000
    Publication date: April 24, 2003
    Inventors: NOBUAKI HAMANAKA, KEN INOUE, KAORU MIKAGI
  • Patent number: 6548421
    Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: April 15, 2003
    Assignee: NEC Corporation
    Inventors: Nobuaki Hamanaka, Ken Inoue, Kaoru Mikagi
  • Publication number: 20030025202
    Abstract: An external electrode in a semiconductor device includes, from the bottom of a wafer, a wiring pad, first and second barrier metal layers, a solder-wetting film and a solder ball. The first barrier metal layer has a tensile internal stress and a granular crystalline structure, whereas the second barrier metal layer has a compressive internal stress and a pillar crystalline structure. The two-layer structure of the barrier metal film has an excellent barrier function against Sn diffusion from the solder ball and reduces the internal stress of the barrier metal film.
    Type: Application
    Filed: July 17, 2002
    Publication date: February 6, 2003
    Applicant: NEC Corporation
    Inventors: Kaoru Mikagi, Akira Furuya, Keisuke Hatano
  • Publication number: 20020093096
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead flee solder is thinly formed on a UBM layer The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: January 14, 2002
    Publication date: July 18, 2002
    Applicant: NEC CORPORATION
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 6413807
    Abstract: Silicide films having a high heat-resistance are formed on a gate electrode, simultaneously with silicide films having good junction leakage characteristics on diffusion layers. A transistor includes a polycrystalline silicon gate electrode, a gate insulating film, a diffusion layer, and sidewalls on a silicon substrate isolated by an element isolation oxide film. A first silicide film and a second silicide film are formed on the gate electrode and on the diffusion layer, respectively. The first silicide film is thicker than the second silicide film.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: July 2, 2002
    Assignee: NEC Corporation
    Inventor: Kaoru Mikagi