Abstract: An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction.

Abstract: A logic LSI is divided into a plurality of functional blocks, and an output portion of each functional block is provided with a buffer circuit with a scan function which can change a function of latching data by a control signal and a function of making an input signal pass intact. The buffer circuit is connected to a test exclusive bus and the test data can be entered directly to the buffer or read out of the buffer. Test patterns are generated in each functional block and diagnosis can be carried out in each functional block. When the functional block is used in other LSI, since the test patterns already generated can be utilized, the time required for generation of test patterns and for the test can be significantly reduced.

Abstract: A logic circuit to be an object for fault simulation is logically modified into a logic circuit configuration using logic gates of a predetermined basic gate form. Pin management data indicative of a correspondence of pins of the logic gates to a position of fault assumption of each of the pins prior to logic modification is formed. Logic simulation is then performed by injecting a fault logic value into the position of fault assumption of each of the pins of the gate of the logic circuit subsequent to the logic modification corresponding to each of the pins prior to the logic modification with reference to the pin management data, thereby implementing a fault simulation for detecting the fault of the logic circuit.

Abstract: In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

Abstract: A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch.