Patents by Inventor Kaoru Nakagawa
Kaoru Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6819607Abstract: In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectivedly operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.Type: GrantFiled: February 10, 2003Date of Patent: November 16, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Mukai, Kaoru Nakagawa
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Publication number: 20030112675Abstract: In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.Type: ApplicationFiled: February 10, 2003Publication date: June 19, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Hideo Mukai, Kaoru Nakagawa
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Patent number: 6567322Abstract: In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.Type: GrantFiled: March 17, 2000Date of Patent: May 20, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Mukai, Kaoru Nakagawa
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Patent number: 6498741Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.Type: GrantFiled: December 21, 2000Date of Patent: December 24, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Katsuki Matsudera, Kazuhide Yoneya, Toshiki Hisada, Masaru Koyanagi, Natsuki Kushiyama, Kaoru Nakagawa, Takahiko Hara
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Patent number: 6496442Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.Type: GrantFiled: February 19, 2002Date of Patent: December 17, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Koyanagi, Kaoru Nakagawa, Takahiko Hara, Satoru Takase
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Patent number: 6466511Abstract: The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.Type: GrantFiled: June 28, 2001Date of Patent: October 15, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Fujita, Kaoru Nakagawa
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Publication number: 20020114209Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.Type: ApplicationFiled: February 19, 2002Publication date: August 22, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Masaru Koyanagi, Kaoru Nakagawa, Takahiko Hara, Satoru Takase
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Patent number: 6370077Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.Type: GrantFiled: April 7, 2000Date of Patent: April 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Koyanagi, Kaoru Nakagawa, Takahiko Hara, Satoru Takase
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Publication number: 20020003748Abstract: The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.Type: ApplicationFiled: June 28, 2001Publication date: January 10, 2002Inventors: Katsuyuki Fujita, Kaoru Nakagawa
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Patent number: 6337826Abstract: A semiconductor integrated circuit is provided with a plurality of selectors, each of which is connected to a corresponding one of a plurality of data lines through which bit data read out from a corresponding one of a plurality of cell array blocks is transmitted, wherein a selector control circuit controls selection operations of the selectors based on a control clock so that the selectors select and output readout data in the order in which the bit data are read out from the corresponding cell array blocks.Type: GrantFiled: March 16, 2000Date of Patent: January 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Seiro Imai, Kaoru Nakagawa
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Publication number: 20010000990Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.Type: ApplicationFiled: December 21, 2000Publication date: May 10, 2001Applicant: Kabushiki Kaisha Toshiba.Inventors: Katsuki Matsudera, Kazuhide Yoneya, Toshiki Hisada, Masaru Koyanagi, Natsuki Kushiyama, Kaoru Nakagawa, Takahiko Hara
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Patent number: 6198649Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.Type: GrantFiled: December 15, 1999Date of Patent: March 6, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Katsuki Matsudera, Kazuhide Yoneya, Toshiki Hisada, Masaru Koyanagi, Natsuki Kushiyama, Kaoru Nakagawa, Takahiko Hara
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Patent number: 5198999Abstract: A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.Type: GrantFiled: September 4, 1991Date of Patent: March 30, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Katsumi Abe, Kaoru Nakagawa, Hiroyuki Koinuma
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Patent number: 5173875Abstract: There is enclosed a semiconductor memory device having an internal circuit including a plurality of memory cells which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive the first output signal to output a second output signal. Power from the same external power supply is delivered to the internal circuit and the output circuit through power supply terminals, and power supply wirings. The power is delivered to the internal circuit through a resistor formed in the middle of the power supply wirings.Type: GrantFiled: November 8, 1990Date of Patent: December 22, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Komatsu, Teruyuki Hiyoshi, Tohru Yoshikawa, Kaoru Nakagawa
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Patent number: 4979146Abstract: In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.Type: GrantFiled: January 27, 1989Date of Patent: December 18, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Sadayuki Yokoyama, Masamichi Asano, Hiroshi Iwahashi, Kaoru Nakagawa
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Patent number: 4967393Abstract: In a nonvolatile semiconductor memory, each of a plurality of memory cells arranged in the form of a matrix includes a p-type semiconductor region, an n-type source connected to the ground potential, an n-type drain formed in a longitudinal direction with respect to the source, a channel region located between the source and the drain, a control gate transversely extending and formed above the channel region, intervening a first insulating film, a floating gate formed in the first insulating film above the channel region, and an erase gate formed in the first insulating film so as to spatially overlap one end of the floating gate. The memory further includes an erase line extending in the longitudinal direction, formed in the first insulating film and connected to the erase gate, and a data line, connected to the drain. First and second memory cells of the plurality of memory cells are arranged to be adjacent to one another in the transverse direction to constitute a first memory cell pair.Type: GrantFiled: January 3, 1990Date of Patent: October 30, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Sadayuki Yokoyama, Kaoru Nakagawa
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Patent number: 4888304Abstract: The present semiconductor device comprises a first semiconductor substrate, an oxide film formed on the substrate and a second semiconductor substrate bonded to the oxide film. In particular, the semiconductor substrate further has a monocrystalline silicon layer which is formed by an epitaxial growth method on the second semiconductor substrate. Circuit elements are formed within the monocrystalline silicon layer.Type: GrantFiled: December 22, 1986Date of Patent: December 19, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kaoru Nakagawa, Yoshio Yamamoto, Nobutaka Matsuoka
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Patent number: 4860327Abstract: A first circuit is made up of a first clocked inverter and a first modified clocked inverter. A second circuit is made up of a second clocked inverter and a second modified clocked inverter. The first circuit has substantially the same circuit arrangement as that of the second circuit. The first circuit operates in response of the output signal from the second circuit, and vice versa.Type: GrantFiled: June 2, 1988Date of Patent: August 22, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kaoru Nakagawa, Katsushi Nagaba
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Patent number: 4856034Abstract: A semiconductor integrated circuit comprises a three-valued logic circuit connected to receive an output signal of a logic circuit to receive at one input a control clock signal and at the other input an input signal, and a flip-flop circuit composed of a clocked inverter to receive the output signal of the three-valued logic circuit, and another inverter.Type: GrantFiled: May 27, 1988Date of Patent: August 8, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Takeuchi, Kaoru Nakagawa
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Patent number: 4706249Abstract: In the semiconductor memory device of the invention, a normal voltage detecting circuit and a high voltage detecting circuit are connected to a terminal for the purpose of receiving a write enable signal. When a signal of normal level is supplied to the terminal, the circuit controls data read or write with respect to a memory cell array in accordance with the level of the write enable signal. An error correction code circuit is rendered operative, and a soft error generated in data read from the memory cell array is corrected. When a high voltage is applied to the terminal, the circuit sets the memory device in the read mode. The circuit detects application of the high voltage to the terminal and supplies a predetermined signal to an ECC control circuit. In response to the signal, the ECC control circuit stops the operation of the ECC circuit. Data without any correction of soft errors is output from the memory device, and testing of hard errors is simplified.Type: GrantFiled: December 3, 1985Date of Patent: November 10, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Kaoru Nakagawa, Mitsugi Ogura, Kenji Natori, Fujio Masuoka