Patents by Inventor Kaoru Shibata
Kaoru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220135327Abstract: An apparatus configured to determine a storage position of a plural type of parts to be assembled to a workpiece corresponding to a plural type of products produced in a predetermined period in accordance with a production schedule, in a storage section having a plural row of storage space facing a lane. The apparatus is configured to store a correspondence relationship between a type of the workpiece corresponding to the products and a type of the parts to be assembled to the workpiece, determine the storage position of the plural type of parts in the storage section based on the correspondence relationship, and to output the storage position. The apparatus determines the storage position so that each of the plural type of parts corresponding to the workpiece is respectively dispersed into each of the plural row of the storage section.Type: ApplicationFiled: February 12, 2020Publication date: May 5, 2022Inventors: Maiko Matsumoto, Kenichi Yamakami, Yuki Kitajima, Kaoru Shibata, Shunsuke Hashiguchi
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Publication number: 20210261792Abstract: An antibacterial coated product includes, on a base material, a coating film of an antibacterial coating material that contains at least composite ceramic powders containing a photocatalytic component, adsorbent component, and metal component, and a binder, wherein the antibacterial activity (JIS Z 2801:2010) of the coating film is 2.0 or higher and the requirement(s) of (1) and/or (2) below is/are satisfied: (1) with respect to the composite ceramic powder in the antibacterial coating material, the volume average dispersed particle diameter (D50) is 250 nm or smaller, and the ratio of the 90% cumulative volume particle diameter (D90) and the volume average dispersed particle diameter (D50), or D90/D50, is 1.5 or lower; and (2) the thickness of the coating film is 80 ?m or smaller and the haze (JIS K 7136:2000) of the antibacterial coated product or coating film is 25 or lower.Type: ApplicationFiled: June 11, 2020Publication date: August 26, 2021Inventors: Kaname KUBOI, Nobushige NUMA, Kaoru SHIBATA
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Patent number: 10547324Abstract: A compression coding method, apparatus, and program suitable for continuously coding pieces of fixed length data are provided. The compression coding method includes: dividing, into columns each with a predetermined bit width, records consisting of a fixed-length bit string that includes one or more fields, pieces of data of the same type being contained in the same field among fields determined in advance; and determining, for each column, a probability of occurrence of a bit value in the column at the same position among a plurality of records, and coding the plurality of records on the basis of the probability of occurrence using an entropy coding method.Type: GrantFiled: December 28, 2018Date of Patent: January 28, 2020Assignees: KOUSOKUYA, INC., DENSO CORPORATIONInventors: Takayuki Suzuki, Kaoru Shibata
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Publication number: 20190140657Abstract: A compression coding method, apparatus, and program suitable for continuously coding pieces of fixed length data are provided. The compression coding method includes: dividing, into columns each with a predetermined bit width, records consisting of a fixed-length bit string that includes one or more fields, pieces of data of the same type being contained in the same field among fields determined in advance; and determining, for each column, a probability of occurrence of a bit value in the column at the same position among a plurality of records, and coding the plurality of records on the basis of the probability of occurrence using an entropy coding method.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Takayuki Suzuki, Kaoru Shibata
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Patent number: 10024516Abstract: An optical module includes a transmitting member. The transmitting member is fixed to a cap member so as to cover a through-hole. On the assumption that the height of one point on a first surface in a state in which the transmitting member is detached from the cap member is zero and the direction toward the outside of the optical module is a positive direction, the amount of warp that is a difference between the displacement at the central point and the displacement at a standard point, on the first surface, corresponding to a reference point, on the projection image, away from a center of gravity by a particular distance is different between a first geodesic line and a second geodesic line, the displacement being a height of the one point in a direction of the optical axis in a state in which the transmitting member is fixed to the cap member. The transmitting member is joined to the cap member at the first surface or the second surface.Type: GrantFiled: July 7, 2017Date of Patent: July 17, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Kyono, Hiromi Nakanishi, Hideyuki Ijiri, Kaoru Shibata
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Patent number: 9887310Abstract: A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2?d1)/d1 is ?3×10?3 or more and 3×10?3 or less, and (d3?d1)/d1 is ?3×10?3 or more and 3×10?3 or less.Type: GrantFiled: January 19, 2015Date of Patent: February 6, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Kei Fujii, Takashi Kyono, Koji Nishizuka, Kaoru Shibata
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Publication number: 20180010763Abstract: An optical module includes a transmitting member. The transmitting member is fixed to a cap member so as to cover a through-hole. On the assumption that the height of one point on a first surface in a state in which the transmitting member is detached from the cap member is zero and the direction toward the outside of the optical module is a positive direction, the amount of warp that is a difference between the displacement at the central point and the displacement at a standard point, on the first surface, corresponding to a reference point, on the projection image, away from a center of gravity by a particular distance is different between a first geodesic line and a second geodesic line, the displacement being a height of the one point in a direction of the optical axis in a state in which the transmitting member is fixed to the cap member. The transmitting member is joined to the cap member at the first surface or the second surface.Type: ApplicationFiled: July 7, 2017Publication date: January 11, 2018Inventors: Takashi Kyono, Hiromi Nakanishi, Hideyuki Ijiri, Kaoru Shibata
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Publication number: 20170294547Abstract: A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order. In the contact layer, a region including a first main surface that is a main surface on a quantum well structure side has a p-type impurity concentration lower than a p-type impurity concentration of a region including a second main surface that is a main surface opposite to the first main surface. A photodiode includes the semiconductor layered structure and an electrode formed on the semiconductor layered structure. A sensor includes the photodiode and a read-out circuit connected to the photodiode.Type: ApplicationFiled: October 21, 2015Publication date: October 12, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kaoru SHIBATA, Koji NISHIZUKA, Suguru ARIKATA, Takashi KYONO, Katsushi AKITA
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Patent number: 9773932Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.Type: GrantFiled: August 18, 2014Date of Patent: September 26, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Koji Nishizuka, Takashi Kyono, Kaoru Shibata, Katsushi Akita
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Patent number: 9698287Abstract: An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of ?0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.Type: GrantFiled: April 23, 2014Date of Patent: July 4, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Kaoru Shibata, Katsushi Akita
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Patent number: 9680040Abstract: A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure.Type: GrantFiled: April 16, 2014Date of Patent: June 13, 2017Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kaoru Shibata, Katsushi Akita, Kei Fujii, Takashi Ishizuka
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Publication number: 20170040477Abstract: A semiconductor layered structure according to the present invention includes a substrate formed of a III-V compound semiconductor; and semiconductor layers disposed on the substrate and formed of III-V compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm?3 or more and 2×1020 cm?3 or less, and the impurity has an activation ratio of 30% or more.Type: ApplicationFiled: December 17, 2014Publication date: February 9, 2017Applicant: Sumitomo Electric Industries, Ltd.Inventors: Suguru Arikata, Takashi Kyono, Koji Nishizuka, Kaoru Shibata, Katsushi Akita
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Publication number: 20160380137Abstract: A light-receiving device includes: a group III-V compound semiconductor substrate having a first main surface; and a light-receiving layer formed on the first main surface, and the group III-V compound semiconductor substrate has a dislocation density of 10000 cm?2 or less. Accordingly, the light-receiving device with low dark current is provided.Type: ApplicationFiled: September 3, 2014Publication date: December 29, 2016Inventors: Kaoru SHIBATA, Kei FUJII, Takashi KYONO, Koji NISHIZUKA, Katsushi AKITA
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Publication number: 20160351742Abstract: A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2?d1)/d1 is ?3×10?3 or more and 3×10?3 or less, and (d3?d1)/d1 is ?3×10?3 or more and 3×10?3 or less.Type: ApplicationFiled: January 19, 2015Publication date: December 1, 2016Inventors: Katsushi Akita, Kei Fujii, Takashi Kyono, Koji Nishizuka, Kaoru Shibata
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Publication number: 20160247951Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.Type: ApplicationFiled: August 18, 2014Publication date: August 25, 2016Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Koji Nishizuka, Takashi Kyono, Kaoru Shibata, Katsushi Akita
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Publication number: 20160056315Abstract: A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure.Type: ApplicationFiled: April 16, 2014Publication date: February 25, 2016Inventors: Kaoru SHIBATA, Katsushi AKITA, Kei FUJII, Takashi ISHIZUKA
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Patent number: 9171978Abstract: A method for producing an epitaxial wafer includes a step of growing an epitaxial layer structure on a III-V semiconductor substrate, the epitaxial layer structure including a III-V semiconductor multiple-quantum well and a III-V semiconductor surface layer, wherein the step of growing the epitaxial layer structure on the substrate is performed such that a lattice mismatch ?? of the multiple-quantum well with respect to the substrate satisfies a range of ?0.13%???<0% or 0%<???+0.13%, the range having a center displaced from zero, and an X-ray rocking curve in a zero-order diffraction peak derived from the multiple-quantum well has a full width at half maximum (FWHM) of 30 seconds or less.Type: GrantFiled: May 22, 2014Date of Patent: October 27, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Kaoru Shibata, Katsushi Akita
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Patent number: 9156626Abstract: High precision work is performed on a work target (workpiece) during conveyance, irrespective of the oscillations accompanying conveyance. A work method includes steps of: predicting a predicted oscillation pattern occurring in a workpiece (W) afterwards from the measurement results of oscillation occurring in the workpiece (W) during conveyance by way of a workpiece conveyance device (2); controlling a robot (131) so as to operate at an oscillation according to the predicted oscillation pattern thus predicted; detecting oscillation occurring in the robot (131) during the step of controlling; and comparing the oscillation occurring in the robot (131) with the predicted oscillation pattern, and in the case of differing, adjusting so that the oscillation of the robot (131) matches the predicted oscillation pattern, in which each of these steps is completed before the robot (131) performs work on the workpiece (W).Type: GrantFiled: July 9, 2013Date of Patent: October 13, 2015Assignee: HONDA MOTOR CO., LTD.Inventors: Kensaku Kaneyasu, Kaoru Shibata, Mitsutaka Igaue, Yushi Aoki, Shoji Matsuda, Kazuki Akami
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Patent number: 9123843Abstract: A semiconductor device includes a semiconductor layer laminate in which a plurality of semiconductor layers are laminated, the semiconductor layer laminate including a light receiving layer, the light receiving layer being grown by a metal-organic vapor phase epitaxy method, the light receiving layer having a cutoff wavelength of more than or equal to 3 ?m and less than or equal to 8 ?m, the semiconductor device having a dark current density of less than or equal to 1×10?1 A/cm2 when a reverse bias voltage of 60 mV is applied at a temperature of ?140° C. Thereby, a semiconductor device which can receive light in a mid-infrared range and has a low dark current is provided.Type: GrantFiled: September 22, 2014Date of Patent: September 1, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Kyono, Katsushi Akita, Kaoru Shibata, Koji Nishizuka, Kei Fujii
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Publication number: 20150115222Abstract: A semiconductor device includes a semiconductor layer laminate in which a plurality of semiconductor layers are laminated, the semiconductor layer laminate including a light receiving layer, the light receiving layer being grown by a metal-organic vapor phase epitaxy method, the light receiving layer having a cutoff wavelength of more than or equal to 3 ?m and less than or equal to 8 ?m, the semiconductor device having a dark current density of less than or equal to 1×10?1 A/cm2 when a reverse bias voltage of 60 mV is applied at a temperature of ?140° C. Thereby, a semiconductor device which can receive light in a mid-infrared range and has a low dark current is provided.Type: ApplicationFiled: September 22, 2014Publication date: April 30, 2015Inventors: Takashi KYONO, Katsushi AKITA, Kaoru SHIBATA, Koji NISHIZUKA, Kei FUJII