Patents by Inventor Kaoru Tahara

Kaoru Tahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8422321
    Abstract: Memory arrays ARY0 and ARY1 each include a regular area 108 and spare area 110. Fuse circuits FS0 and FS1 each store a relief address. Relief determination circuits RJ0 and RJ1 are provided so as to correspond to the fuse circuits FS0 and FS1, respectively. The relief determination circuits RJ0 and RJ1 each determine whether a designation address is the relief address or not. An access control circuit AC specifies an access destination from the memory array ARY0 or ARY1 according to the determination results. When it is determined by the relief determination circuit RJ0 that the designation address corresponds to the relief address, the access control circuit AC selects one of the memory arrays ARY0 and ARY1 according to CX13T<1:0> and selects the spare area 110 included in the selected memory array ARY as an access target.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 16, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kaoru Tahara
  • Publication number: 20110188332
    Abstract: Memory arrays ARY0 and ARY1 each include a regular area 108 and spare area 110. Fuse circuits FS0 and FS1 each store a relief address. Relief determination circuits RJ0 and RJ1 are provided so as to correspond to the fuse circuits FS0 and FS1, respectively. The relief determination circuits RJ0 and RJ1 each determine whether a designation address is the relief address or not. An access control circuit AC specifies an access destination from the memory array ARY0 or ARY1 according to the determination results. When it is determined by the relief determination circuit RJ0 that the designation address corresponds to the relief address, the access control circuit AC selects one of the memory arrays ARY0 and ARY1 according to CX13T<1:0> and selects the spare area 110 included in the selected memory array ARY as an access target.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 4, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kaoru Tahara
  • Patent number: 7355918
    Abstract: In a refresh method of a semiconductor memory device, two output pulses having different division ratios are generated by dividing a clock pulse. One of them having a shorter cycle is used to execute a short cycle refresh operation after a self-refresh operation starts. After a predetermined period of time elapses, the other having a longer cycle is used to execute a long cycle refresh operation. When a read/write operation is executed continuously and an element temperature increases, the charges stored in a capacitor of a memory cell are liable to decrease. Accordingly, when an operation mode is switched to a self-refresh mode just after the read/write operation is executed continuously, a refresh operation must be executed at a cycle shorter than an ordinary cycle until temperature is stabilized. After the predetermined period of time elapses, the refresh operation is executed at an ordinary long cycle.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: April 8, 2008
    Assignee: Elpida Memory, Inc.
    Inventor: Kaoru Tahara
  • Publication number: 20060104140
    Abstract: In a refresh method of a semiconductor memory device, two output pulses having different division ratios are generated by dividing a clock pulse. One of them having a shorter cycle is used to execute a short cycle refresh operation after a self-refresh operation starts. After a predetermined period of time elapses, the other having a longer cycle is used to execute a long cycle refresh operation. When a read/write operation is executed continuously and an element temperature increases, the charges stored in a capacitor of a memory cell are liable to decrease. Accordingly, when an operation mode is switched to a self-refresh mode just after the read/write operation is executed continuously, a refresh operation must be executed at a cycle shorter than an ordinary cycle until temperature is stabilized. After the predetermined period of time elapses, the refresh operation is executed at an ordinary long cycle.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 18, 2006
    Applicant: Elpida Memory, Inc.
    Inventor: Kaoru Tahara