Patents by Inventor Kaoruko Yamada

Kaoruko Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit
    Patent number: 5352942
    Abstract: A gate array chip is supplied with an operation voltage of 5V. A logic circuit formed of gate arrays in a chip is operated on an operation voltage of 3.3V. The potential of 3.3V is derived by lowering the potential of 5V by use of a voltage lowering circuit disposed in the chip. A level shifter and a converter are disposed in an I/O peripheral circuit to shift the signal level by use of the chip external signal and chip internal signal so that a signal of 5V amplitude can be input or output.
    Type: Grant
    Filed: January 24, 1992
    Date of Patent: October 4, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Tanaka, Toshikazu Sei, Teruo Kobayashi, Kaoruko Yamada