Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Abstract: A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities using dynamic buffer allocation. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets.

Abstract: An architecture for a high performance IPSEC accelerator. The architecture includes components for scanning fields of packets, programming an IPSEC services device according to the scanned fields, and modifying the scanned packet with an output from the IPSEC security services device. Preferably, the architecture is implemented in hardware, and attached to a host machine. Hardware devices, fast in comparison to software processing and network speeds, allows the computationally intensive IPSEC processes to be completed in real-time and reduce or eliminate bottlenecks in the path of a packet being sent or received to/from a network.

Abstract: A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities.

Abstract: A hardware packet accelerator parses incoming packets to retrieve header data for building a frame status and for verifying the incoming packets are part of an established connection with a host. The accelerator includes a connection database that allows retrieval of connection information based on an index constructed from a hashed TCP connection address. The frame status comprises information needed to perform packet re-assembly and is stored in a memory that is local (directly accessible) by a processing device that performs the packet re-assembly. Among other advantages, the processing device does not need to read packet header data from a packet buffer, saving large amounts of header data retrieval time.

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.