Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.

Abstract: A memory may require a buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.

Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.

Abstract: Disclosed herein is a method for identifying a constellation of alignment marks within an arrangement of computer readable marks in an image (1412), the arrangement of computer readable marks (1412) including alignment marks (1401-1406) and data carrying marks (1407-1410). The alignment marks (1401-1406) define a reference grid within the arrangement of computer readable marks and the data carrying marks (1407-1410) are modulated with respect to the reference grid to encode data. The method selects at least two marks (1501, 1502) from the arrangement of computer readable marks and determines a rotation center with reference to the selected marks (1501, 1502). The method then determines rotated positions for the selected marks by rotating each of the selected marks by a predetermined angle about the rotation center.

Abstract: Disclosed herein is a method for identifying a constellation of alignment marks within an arrangement of computer readable marks in an image (1412), the arrangement of computer readable marks (1412) including alignment marks (1401-1406) and data carrying marks (1407-1410). The alignment marks (1401-1406) define a reference grid within the arrangement of computer readable marks and the data carrying marks (1407-1410) are modulated with respect to the reference grid to encode data. The method selects at least two marks (1501, 1502) from the arrangement of computer readable marks and determines a rotation centre with reference to the selected marks (1501, 1502). The method then determines rotated positions for the selected marks by rotating each of the selected marks by a predetermined angle about the rotation centre.

Abstract: A memory may require buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs, which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.