Patents by Inventor Kapil Garg
Kapil Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250061276Abstract: A system for interaction pattern recognition receives an input primary interaction and accesses clusters indicating interaction group patterns. Each cluster includes a respective primary interaction and secondary interactions linked to that primary interaction. Each cluster is identified by a respective non-fungible token.Type: ApplicationFiled: August 14, 2023Publication date: February 20, 2025Inventors: Nitin Bansal, Kapil Juneja, Rajalakshmi Arumugam, Kumaraguru Mohan, Venkatesh Polneedi, Anil Garg, Gaurav Kumar Kashyap
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Publication number: 20240386659Abstract: Systems, methods, and computer-readable media are provided for a color metadata buffer for three-dimensional reconstruction (3DR). In some examples, a method for 3DR can include, during a first operational pass, projecting a block (e.g., a voxel) onto a depth frame, performing depth integration on the block to produce an updated block, and storing color integration metadata for the block in a color metadata buffer. The method can also include, during a second operational pass, projecting the updated depth block onto a color frame, and performing color integration on the updated depth block using the color integration metadata to produce an updated depth and color block.Type: ApplicationFiled: May 16, 2023Publication date: November 21, 2024Inventors: Kapil GARG, Sriganesh BALAKUMAR, Yifan ZHANG
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Patent number: 12149720Abstract: Systems and techniques are provided for caching misaligned pixel tiles. A method includes determining a first codec region including a first region of a frame; determining whether pixels of a first version of a pixel tile were stored in a cache while coding blocks from a second codec region, the pixel tile corresponding to a location within the frame; based on whether the pixels were stored in the cache, determining whether to read the first version of the pixel tile from the cache or retrieve a second version of the pixel tile from a memory device, the second version of the pixel tile including pixels from the first codec region that are not in the first version of the pixel tile; and coding a block based on the first version of the pixel tile read from the cache or second version of the pixel tile retrieved from the memory device.Type: GrantFiled: June 10, 2022Date of Patent: November 19, 2024Assignee: QUALCOMM INCORPORATEDInventors: Sriganesh Balakumar, Kapil Garg, Gaurav Avinash Patil, Rajesh Chowdary Chitturi, Prasanth Gomatam, Sravan Kumar Gopanapalle
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Publication number: 20240357121Abstract: An apparatus configured to decode video data includes a shared memory and one or more processors configured to execute a plurality of video decoding cores. At least one of the plurality of video decoding cores in communication with the shared memory, and each of plurality of video decoding cores are configured to track completion of decoding samples of one or more regions of a frame of video data, write information to the shared memory, the information indicative of the completion of decoding the samples of the one or more regions of the frame of video data, read, prior to decoding a subsequent region of the frame of video data, the information in the shared memory, and determine whether to decode the subsequent region of the frame of video data based on the information.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Inventors: Gaurav Avinash Patil, Kapil Garg, Rajesh Chowdary Chitturi, Prasanth Gomatam
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Patent number: 12063367Abstract: An apparatus configured to decode video data includes a shared memory and one or more processors configured to execute a plurality of video decoding cores. At least one of the plurality of video decoding cores in communication with the shared memory, and each of plurality of video decoding cores are configured to track completion of decoding samples of one or more regions of a frame of video data, write information to the shared memory, the information indicative of the completion of decoding the samples of the one or more regions of the frame of video data, read, prior to decoding a subsequent region of the frame of video data, the information in the shared memory, and determine whether to decode the subsequent region of the frame of video data based on the information.Type: GrantFiled: July 27, 2022Date of Patent: August 13, 2024Assignee: QUALCOMM INCORPORATEDInventors: Gaurav Avinash Patil, Kapil Garg, Rajesh Chowdary Chitturi, Prasanth Gomatam
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Patent number: 12010325Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.Type: GrantFiled: October 20, 2022Date of Patent: June 11, 2024Assignee: QUALCOMM INCORPORATEDInventors: Kapil Garg, Gaurav Avinash Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
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Patent number: 11960721Abstract: A method for dynamically storing keys and values includes receiving a request for storing one or more keys in a key value Solid State drive (KV-SSD). The method further includes performing a storage operation for storing each key of the one or more keys in a node of a data structure of the KV-SSD. The storage operation includes allocating a first region in the node for storing the key, such that a size of the first region is equal to a size of the key. The storage operation further includes allocating a second region in the node for storing key metadata associated with the key, such that the second region is of a predetermined size. The storage operation further includes storing the key in the first region and the key metadata in the second region of the node.Type: GrantFiled: July 7, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Srikanth Tumkur Shivanand, Kapil Garg, Paul Justin K, Sarath Chandra Reddy, Sri Gobicca Kms
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Publication number: 20240040125Abstract: An apparatus configured to decode video data includes a shared memory and one or more processors configured to execute a plurality of video decoding cores. At least one of the plurality of video decoding cores in communication with the shared memory, and each of plurality of video decoding cores are configured to track completion of decoding samples of one or more regions of a frame of video data, write information to the shared memory, the information indicative of the completion of decoding the samples of the one or more regions of the frame of video data, read, prior to decoding a subsequent region of the frame of video data, the information in the shared memory, and determine whether to decode the subsequent region of the frame of video data based on the information.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Gaurav Avinash Patil, Kapil Garg, Rajesh Chowdary Chitturi, Prasanth Gomatam
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Publication number: 20230403404Abstract: Systems and techniques are provided for caching misaligned pixel tiles. A method includes determining a first codec region including a first region of a frame; determining whether pixels of a first version of a pixel tile were stored in a cache while coding blocks from a second codec region, the pixel tile corresponding to a location within the frame; based on whether the pixels were stored in the cache, determining whether to read the first version of the pixel tile from the cache or retrieve a second version of the pixel tile from a memory device, the second version of the pixel tile including pixels from the first codec region that are not in the first version of the pixel tile; and coding a block based on the first version of the pixel tile read from the cache or second version of the pixel tile retrieved from the memory device.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Inventors: Sriganesh BALAKUMAR, Kapil GARG, Gaurav Avinash PATIL, Rajesh Chowdary CHITTURI, Prasanth GOMATAM, Sravan Kumar GOPANAPALLE
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Publication number: 20230059060Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.Type: ApplicationFiled: October 20, 2022Publication date: February 23, 2023Inventors: Kapil Garg, Gaurav Avinash Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
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Publication number: 20230019465Abstract: A method for dynamically storing keys and values includes receiving a request for storing one or more keys in a key value Solid State drive (KV-SSD). The method further includes performing a storage operation for storing each key of the one or more keys in a node of a data structure of the KV-SSD. The storage operation includes allocating a first region in the node for storing the key, such that a size of the first region is equal to a size of the key. The storage operation further includes allocating a second region in the node for storing key metadata associated with the key, such that the second region is of a predetermined size. The storage operation further includes storing the key in the first region and the key metadata in the second region of the node.Type: ApplicationFiled: July 7, 2022Publication date: January 19, 2023Inventors: Srikanth Tumkur SHIVANAND, Kapil GARG, Paul Justin K, Sarath Chandra REDDY, Sri Gobicca KMS
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Patent number: 11516477Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.Type: GrantFiled: February 11, 2021Date of Patent: November 29, 2022Assignee: Qualcomm IncorporatedInventors: Kapil Garg, Gaurav Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
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Publication number: 20220256167Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Kapil Garg, Gaurav Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
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Patent number: 11093143Abstract: Methods and systems for managing Key-Value Solid State Drives (KV SSDs). A method includes writing, by a host processor, at least one Key-value pair of at least one write command to at least one KV SSD of a plurality of KV SSDs of at least one RAID group based on at least one of slab information, available space and load. Further, the method includes reading, by the host processor, at least one value from the at least one KV SSD of the plurality of KV SSDs for at least one key of at least one read command using at least one of a consistent hashing function and slab information.Type: GrantFiled: September 13, 2019Date of Patent: August 17, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Srikanth Tumkur Shivanand, Vikram Singh, Paul Justin K, Jayantha Gopala, Kapil Garg
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Publication number: 20210011634Abstract: Methods and systems for managing Key-Value Solid State Drives (KV SSDs). A method includes writing, by a host processor, at least one Key-value pair of at least one write command to at least one KV SSD of a plurality of KV SSDs of at least one RAID group based on at least one of slab information, available space and load. Further, the method includes reading, by the host processor, at least one value from the at least one KV SSD of the plurality of KV SSDs for at least one key of at least one read command using at least one of a consistent hashing function and slab information.Type: ApplicationFiled: September 13, 2019Publication date: January 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Srikanth TUMKUR SHIVANAND, Vikram Singh, Paul Justin K, Jayantha Gopala, Kapil Garg