Abstract: An array of metal bodies are attached to a metal carrier by forming Metal bodies form metal inter-diffusions with carrier. The metal bodies are coined to form flattened body ends. A polymeric adhesive precursor is disposed onto the array and a semiconductor chip having a first surface including circuitry and an opposite second surface free of circuitry is attached to the adhesive precursor so that the second chip surface is in contact with the flattened ends of the arrayed metal bodies, which stop at the second surface.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).

Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).

Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).