Abstract: Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.

Abstract: A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.