Abstract: A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

Abstract: A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Abstract: A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.

Abstract: A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Abstract: A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.

Abstract: A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

Abstract: A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.

Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.

Abstract: A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.

Abstract: An integrated analog and digital adaptive platform includes: a plurality of adaptive analog blocks, each of the plurality of adaptive analog blocks being integrated with a respective digital wrapper; and a programmable digital fabric configured to programmably connect one or more of the plurality of adaptive analog blocks by connecting a plurality of digital wrappers integrated with the one or more of the plurality of adaptive analog blocks. The plurality of adaptive analog blocks that are programmably connected using the programmable digital fabric provide one or more programmable analog functions.

Abstract: A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Abstract: A structure and a method provide a programmable logic device including a number of generic logic blocks and one or more application-specific block. Such application-specific block implements a specific function, such as a register file or a memory array. In one embodiment, the application specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks using a global routing resource integrates into a programmable logic device functions otherwise difficult to implement using only generic logic blocks.

Abstract: A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor is provided at each intersection of a horizontal line and a vertical line. Each line is connected to a pin through a programmable I/O cell which includes a floating gate transistor. Each I/O cell can be programmed to configure the corresponding pin as an input pin or as an inverting or non-inverting output pin. The I/O cell can also be programmed to tri-state the pin or to fix the pin at a high or low voltage level. Each input pin can be connected to more than one output pins. A TTL-to-CMOS translator in each I/O cell is provided in the output section of the cell to reduce the translator output load and make the load, and hence the speed and power consumption of the switch, less dependent on the switch programming.

Abstract: A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.

Abstract: The disclosed structure and method route an input signal received at an input/output pin through multiple input/output cells to a routing resource. In one embodiment, each input/output cell can be programmed to provide either a combinatorial input signal or a registered input signal. Increased flexibility is achieved by routing the registered input signal or the combinatorial input signal of each cell to a routing resource via one or more I/O cells.

Abstract: An integrated circuit programmable sequencing element apparatus on a single chip is provided which includes a PROM including first signal receiving circuitry and second signal providing circuitry; at least one feedback signal providing circuitry responsive to at least one second signal for providing at least one feedback signal; at least one input signal providing circuitry for providing at least one input signal; at least one control signal providing circuitry for providing at least one control signal; at least one programmable sequencing element circuitry for receiving said at least one control signal and the at least one input signal and for providing at least one programmable sequencing element signal; and selection circuitry for selecting at least between the at least one programmable sequencing element signal and the at least one feedback signal and for providing at least one selected signal to the first signal receiving circuitry.

Abstract: A macrocell is provided for use in logic circuits which is capable of being configured into any one of six different states so as to replicate an X-type output architecture, an L-type output architecture and a number of hybrid architectures which encompass features from one or both of these types.