Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Storage devices are often configured to receive and process commands from a host-computing device. These commands can vary in size and priority with larger sizes of command data being processed by storage devices more frequently. As these sizes increase, more situations occur when newly received high priority commands are received and ready for processing, but must wait for the current data associated with a normal priority command to be fetched and/or processed. Traditionally, the high priority command must wait, no matter how long, until the currently underway normal priority command is fetched and/or completed. However, methods and system described herein allow for the interruption of normal priority data fetching prior to completion. In this way, lower latencies may be achieved as high priority commands are not required to wait for processing. The previously fetched data may be dumped and re-fetched again or may be stored until normal operations can resume.

Abstract: Storage devices are often configured to receive and process commands from a host-computing device. These commands can vary in size and priority with larger sizes of command data being processed by storage devices more frequently. As these sizes increase, more situations occur when newly received high priority commands are received and ready for processing, but must wait for the current data associated with a normal priority command to be fetched and/or processed. Traditionally, the high priority command must wait, no matter how long, until the currently underway normal priority command is fetched and/or completed. However, methods and system described herein allow for the interruption of normal priority data fetching prior to completion. In this way, lower latencies may be achieved as high priority commands are not required to wait for processing. The previously fetched data may be dumped and re-fetched again or may be stored until normal operations can resume.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. As the write requests for the related write group are processed, the related write request indicator is updated to allow incomplete write groups to be identified in the event of a failure.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Aspects of the disclosure provide a data storage device that includes a non-volatile memory and a controller. The controller includes a memory and a processor. The processor is configured to determine whether there is a deadlock in a communication link between the data storage apparatus and a host; and transmit, when there is a deadlock in the communication link between the data storage apparatus and the host, a recovery command to the host to re-establish a link layer connection between the data storage apparatus and the host.

Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. As the write requests for the related write group are processed, the related write request indicator is updated to allow incomplete write groups to be identified in the event of a failure.

Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. An event notification is sent to a host system when the related write request indicator indicates that the group was incomplete at the time of a data loss event.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. An event notification is sent to a host system when the related write request indicator indicates that the group was incomplete at the time of a data loss event.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Aspects of the disclosure provide a data storage device that includes a non-volatile memory and a controller. The controller includes a memory and a processor. The processor is configured to determine whether there is a deadlock in a communication link between the data storage apparatus and a host; and transmit, when there is a deadlock in the communication link between the data storage apparatus and the host, a recovery command to the host to re-establish a link layer connection between the data storage apparatus and the host.

Abstract: An apparatus includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller includes a processor configured to perform a first operation and a second operation and further includes an access device interface configured to communicate with a first device. The memory controller further includes a wireless interface configured to communicate with a second device to transfer data associated with the second operation to the second device to enable performance at the second device of one or more tasks of the second operation.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: An apparatus includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller includes a processor configured to perform a first operation and a second operation and further includes an access device interface configured to communicate with a first device. The memory controller further includes a wireless interface configured to communicate with a second device to transfer data associated with the second operation to the second device to enable performance at the second device of one or more tasks of the second operation.

Abstract: An electronic device including a communication interface and a command buffer coupled to the communication interface. The communication interface is configured to receive commands from a plurality of initiator devices, and the command buffer is configured to store the commands. The electronic device further includes a command buffer management module coupled to the command buffer. The command buffer management module is configured to generate a message indicating a remaining allowed storage size associated with the command buffer. The communication interface is further configured to enable communication of the message to a particular initiator device of the plurality of initiator devices. The message may enable the particular initiator device to hold off on sending one or more other commands to the command buffer if the remaining allowed storage size fails to satisfy a threshold storage size.

Abstract: A memory system and method for fast firmware download are provided. In one embodiment, a memory system is presented comprising non-volatile memory, volatile memory, and a controller. The controller is configured to receive a boot loader and firmware; store the boot loader and firmware in the volatile memory; execute the boot loader, wherein executing the boot loader causes the controller to read the firmware from the volatile memory, decompress the firmware, and store the decompressed firmware in the volatile memory; and copy the compressed firmware from the volatile memory to the non-volatile memory. Other embodiments are provided.

Abstract: An electronic device including a communication interface and a command buffer coupled to the communication interface. The communication interface is configured to receive commands from a plurality of initiator devices, and the command buffer is configured to store the commands. The electronic device further includes a command buffer management module coupled to the command buffer. The command buffer management module is configured to generate a message indicating a remaining allowed storage size associated with the command buffer. The communication interface is further configured to enable communication of the message to a particular initiator device of the plurality of initiator devices. The message may enable the particular initiator device to hold off on sending one or more other commands to the command buffer if the remaining allowed storage size fails to satisfy a threshold storage size.

Abstract: The invention may be embodied in a multiple-disk data storage system including a controller module that initiates an optimization algorithm to set maximum queue depth of each disk of the data storage system to desired queue depth of each disk. Desired queue depth of each disk may be associated with performance factors including, but not limited to, input/output operations per second (IOPs), average response time, and/or maximum response time of each disk. Desired queue depth of each disk may be further associated with priority rankings of performance factors.