Patents by Inventor Kapil Suri

Kapil Suri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared memory switch fabric system and method
    Patent number: 10491543
    Abstract: A system and method of transferring cells through a switch fabric having a shared memory crossbar switch, a plurality of cell receive blocks and a plurality of cell transmit blocks. The system determines, based on a number of cells queued up in respective output buffers in the cell transmit blocks, output buffers in the cell transmit blocks that can receive cells on a low latency path. The cells transferred include first cells that can be transferred on the low latency path and second cells that cannot be transferred via the low latency path. The first cells are transferred via a bypass mechanism in shared memory to the output buffers. The second cells are transferred by writing the second cells to shared memory, reading the second cells from shared memory and transferring the second cells read from shared memory to the output buffers in the cell transmit blocks.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 26, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Rahul Wagh, Kapil Suri, Gurjeet Singh, Harshad B Agashe, Srihari Raju Vegesna, Dinesh Jaiswal
  • Shared memory switch fabric system and method
    Patent number: 9985912
    Abstract: A system and method of transferring cells through a switch fabric having a shared memory crossbar switch, a plurality of cell receive blocks and a plurality of cell transmit blocks. The system determines, based on a number of cells queued up in respective output buffers in the cell transmit blocks, output buffers in the cell transmit blocks that can receive cells on a low latency path. The cells transferred include first cells that can be transferred on the low latency path and second cells that cannot be transferred via the low latency path. The first cells are transferred via a bypass mechanism in shared memory to the output buffers. The second cells are transferred by writing the second cells to shared memory, reading the second cells from shared memory and transferring the second cells read from shared memory to the output buffers in the cell transmit blocks.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 29, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Rahul Wagh, Kapil Suri, Gurjeet Singh, Harshad B Agashe, Srihari R. Vegesna, Dinesh Jaiswal