Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.

Abstract: A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.

Abstract: An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.

Abstract: A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.