Patents by Inventor Kapila Wijekoon
Kapila Wijekoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120315756Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: ApplicationFiled: March 15, 2012Publication date: December 13, 2012Inventors: Timothy W. Weidman, Arulkumar Shanmugasundram, Kapila Wijekoon, Schubert S. Chu, Frederick C. Wu, Kavita Shah
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Patent number: 8129212Abstract: Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate, wetting the substrate with an alkaline solution comprising a wetting agent, and forming a textured surface with a structure having a depth about 1 ?m to about 10 ?m on the substrate. In another embodiment, a method of performing a substrate texture process includes providing crystalline silicon substrate, pre-cleaning the substrate in a HF aqueous solution, wetting the substrate with a KOH aqueous solution comprising polyethylene glycol (PEG) compound, and forming a textured surface with a structure having a depth about 3 ?m to about 8 ?m on the substrate.Type: GrantFiled: March 23, 2009Date of Patent: March 6, 2012Assignee: Applied Materials, Inc.Inventors: Kapila Wijekoon, Rohit Mishra, Michael P Stewart, Timothy Weidman, Hari Ponnekanti, Tristan R. Holtam
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Publication number: 20110272625Abstract: Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate, wetting the substrate with an alkaline solution comprising a wetting agent, and forming a textured surface with a structure having a depth about 1 ?m to about 10 ?m on the substrate. In another embodiment, a method of performing a substrate texture process includes providing crystalline silicon substrate, pre-cleaning the substrate in a HF aqueous solution, wetting the substrate with a KOH aqueous solution comprising polyethylene glycol (PEG) compound, and forming a textured surface with a structure having a depth about 3 ?m to about 8 ?m on the substrate.Type: ApplicationFiled: July 13, 2011Publication date: November 10, 2011Inventors: Kapila Wijekoon, Rohit Mishra, Michael P. Stewart, Timothy Weidman, Hari Ponnekanti, Tristan R. Holtam
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Patent number: 7651934Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: GrantFiled: March 20, 2006Date of Patent: January 26, 2010Assignee: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Timothy W. Weidman, Arulkumar Shanmugasundram, Nicolay Y. Kovarsky, Kapila Wijekoon
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Publication number: 20090280597Abstract: Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate, wetting the substrate with an alkaline solution comprising a wetting agent, and forming a textured surface with a structure having a depth about 1 ?m to about 10 ?m on the substrate. In another embodiment, a method of performing a substrate texture process includes providing crystalline silicon substrate, pre-cleaning the substrate in a HF aqueous solution, wetting the substrate with a KOH aqueous solution comprising polyethylene glycol (PEG) compound, and forming a textured surface with a structure having a depth about 3 ?m to about 8 ?m on the substrate.Type: ApplicationFiled: March 23, 2009Publication date: November 12, 2009Inventors: Kapila Wijekoon, Rohit Mishra, Michael P. Stewart, Timothy Weidman, Hari Ponnekanti, Tristan R. Holtam
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Publication number: 20070099422Abstract: Embodiments of the invention provide a method for depositing a copper material on a substrate by an electroless deposition process and also provide a composition of an electroless deposition solution. In one embodiment, the copper material is deposited from an electroless copper solution that contains an additive, such as an inhibitor, to promote a bottom-up fill process. In one aspect, the field of the substrate may be maintained free of copper material or substantially free of copper material during the electroless deposition process. Prior to the electroless deposition process for forming the copper material, a barrier layer may be deposited on the substrate, and thereafter, a ruthenium layer may be deposited thereon. In one example, the copper material is formed during a bottom-up, electroless deposition process directly on the ruthenium layer. Alternatively, a seed layer may be formed on the ruthenium layer prior to depositing the copper material.Type: ApplicationFiled: October 28, 2005Publication date: May 3, 2007Inventors: Kapila Wijekoon, Timothy Weidman, Arulkumar Shanmugasundram
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Publication number: 20070004201Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: ApplicationFiled: March 20, 2006Publication date: January 4, 2007Inventors: Dmitry Lubomirsky, Timothy Weidman, Arulkumar Shanmugasundram, Nicolay Kovarsky, Kapila Wijekoon
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Patent number: 7153188Abstract: The carrier head has a base and a substrate backing structure for holding a substrate against a polishing surface during polishing. The substrate backing structure is connected to the base and includes an external surface that contacts a backside of the substrate during polishing. The substrate backing structure also includes a resistive heating system to distribute heat over an area of the external surface and at least one thermally conductive membrane. The external surface is a first surface of the at least one thermally conductive membrane, and the resistive heating system is integrated within one of the at least one thermally conductive membrane.Type: GrantFiled: October 7, 2005Date of Patent: December 26, 2006Assignee: Applied Materials, Inc.Inventors: Steven M. Zuniga, Hung Chih Chen, Stan D. Tsai, Kapila Wijekoon, Fred C. Redeker, Rajeev Bajaj
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Publication number: 20060251800Abstract: Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process.Type: ApplicationFiled: March 20, 2006Publication date: November 9, 2006Inventors: Timothy Weidman, Kapila Wijekoon, Zhize Zhu, Avgerinos Gelatos, Amit Khandelwal, Arulkumar Shanmugasundram, Michael Yang, Fang Mei, Farhad Moghadam
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Publication number: 20060246699Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: ApplicationFiled: March 20, 2006Publication date: November 2, 2006Inventors: Timothy Weidman, Arulkumar Shanmugasundram, Kapila Wijekoon, Schubert Chu, Frederick Wu, Kavita Shah
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Patent number: 7070480Abstract: Method and apparatus for polishing substrates. A chemical mechanical polishing article comprises a body and a patterned surface. The patterned surface comprises a plurality of slurry distribution grooves and a plurality of islands on the body. Each of the plurality of the islands comprises a base portion, a polishing surface disposed thereon, and a contoured surface disposed therebetween. The base portion comprises one or more sidewalls defining at least a portion of the plurality of slurry distribution grooves. The polishing surface is smaller than the base portion, the difference therebetween attributable to the contoured surface. In a particular embodiment, conductive materials and low k dielectric films are polished with reduced or minimum substrate surface damage.Type: GrantFiled: October 10, 2002Date of Patent: July 4, 2006Assignee: Applied Materials, Inc.Inventors: Yongsik Moon, Kapila Wijekoon
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Patent number: 6960521Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.Type: GrantFiled: September 13, 2004Date of Patent: November 1, 2005Assignee: Applied Materials, Inc.Inventors: Yongsik Moon, David Mai, Kapila Wijekoon, Rajeev Bajaj, Rahul Surana, Yongqi Hu, Tony S. Kaushal, Shijian Li, Jui-Lung Li, Shi-Ping Wang, Gary Lam, Fred C. Redeker
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Publication number: 20050032381Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.Type: ApplicationFiled: September 13, 2004Publication date: February 10, 2005Inventors: Yongsik Moon, David Mai, Kapila Wijekoon, Rajeev Bajaj, Rahul Surana, Yongqi Hu, Tony Kaushal, Shijian Li, Jui-Lung Li, Shi-Ping Wang, Gary Lam, Fred Redeker
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Patent number: 6790768Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.Type: GrantFiled: December 18, 2001Date of Patent: September 14, 2004Assignee: Applied Materials Inc.Inventors: Yongsik Moon, David Mai, Kapila Wijekoon, Rajeev Bajaj, Rahul Surana, Yongqi Hu, Tony S. Kaushal, Shijian Li, Jui-Lung Li, Shi-Ping Wang, Gary Lam, Fred C. Redeker
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Patent number: 6638143Abstract: Ion exchange materials are employed in CMP methodologies to polish or thin a semiconductor substrate or a layer thereon. Embodiments include a polishing pad having an ion exchange material thereon and polishing a semiconductor substrate or a layer thereon with the polishing pad or a CMP composition including an ion exchange material therein and polishing the substrate or a layer thereon with the CMP composition or both.Type: GrantFiled: December 14, 2000Date of Patent: October 28, 2003Assignee: Applied Materials, Inc.Inventors: Yuchun Wang, Stan D. Tsai, Kapila Wijekoon, Rajeev Bajaj, Fred C. Redeker
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Patent number: 6620027Abstract: Methods and apparatus for planarizing a substrate surface having copper containing materials thereon is provided. In one aspect, the invention provides a system for processing substrates comprising a first platen adapted for polishing a substrate with a hard polishing pad disposed on the first platen, a second platen adapted for polishing a substrate with a hard polishing pad disposed on the second platen, and a third platen adapted for polishing a substrate with a hard polishing pad disposed on the third platen. In another aspect, the invention provides a method for planarizing a substrate surface by the system described above including substantially removing bulk copper containing materials on the first platen, removing residual copper containing materials on the second platen, and then removing a barrier layer on the third platen. A computer readable program may also be provided for performing the methods described herein.Type: GrantFiled: January 9, 2002Date of Patent: September 16, 2003Assignee: Applied Materials Inc.Inventors: Ajoy Zutshi, Rajeev Bajaj, Fred C. Redeker, Yutao Ma, Kapila Wijekoon
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Publication number: 20030114084Abstract: Method and apparatus for polishing substrates. A chemical mechanical polishing article comprises a body and a patterned surface. The patterned surface comprises a plurality of slurry distribution grooves and a plurality of islands on the body. Each of the plurality of the islands comprise a base portion and a tip portion disposed on the base portion. The base portion comprises a sidewall defining at least a portion of the plurality of slurry distribution grooves and the tip portion has a decreasing diameter from the base portion to an upper polishing surface. In a particular embodiment, conductive materials and low k dielectric films are polished with reduced or minimum substrate surface damage and peeling.Type: ApplicationFiled: October 10, 2002Publication date: June 19, 2003Inventors: Yongsik Moon, Kapila Wijekoon
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Patent number: 6572453Abstract: A polishing method is provided which simultaneously supplies both a polishing fluid and a conditioning fluid to a polishing pad, while a substrate is in moving contact with the polishing pad.Type: GrantFiled: May 18, 2000Date of Patent: June 3, 2003Assignee: Applied Materials, Inc.Inventors: Kapila Wijekoon, Stan D. Tsai, Yuchun Wang, Doyle E. Bennett, Fred C. Redeker, Madhavi Chandrachood, Brian J. Brown
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Patent number: 6561873Abstract: Dishing in chemical mechanical polishing (CMP) is reduced by introducing a material that balances electrochemical forces. In a first embodiment of the invention, a polishing pad having copper material in grooves on the polishing pad surface is used in the polishing process to reduce dishing. In a second embodiment of the invention, the polishing pad has perforations with copper fillings. In a third embodiment of the invention, a copper retaining ring on the polishing head introduces copper material to the CMP process to reduce dishing. In a fourth embodiment of the invention, a conditioning plate of copper is used in the polishing apparatus. In a fifth embodiment of the invention, additional copper features are placed on the substrate to be polished. The polishing of the additional features introduces copper steadily through the polishing process. In a sixth embodiment of the invention, copper compounds are added to the polish slurry.Type: GrantFiled: March 8, 2002Date of Patent: May 13, 2003Assignee: Applied Materials, Inc.Inventors: Stan D. Tsai, Yuchun Wang, Kapila Wijekoon, Rajeev Bajaj, Fred C. Redeker
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Patent number: 6537144Abstract: Dishing in chemical mechanical polishing (CMP) is reduced by introducing a material that balances electrochemical forces. In a first embodiment of the invention, a polishing pad having copper material in grooves on the polishing pad surface is used in the polishing process to reduce dishing. In a second embodiment of the invention, the polishing pad has perforations with copper fillings. In a third embodiment of the invention, a copper retaining ring on the polishing head introduces copper material to the CMP process to reduce dishing. In a fourth embodiment of the invention, a conditioning plate of copper is used in the polishing apparatus. In a fifth embodiment of the invention, additional copper features are placed on the substrate to be polished. The polishing of the additional features introduces copper steadily through the polishing process. In a sixth embodiment of the invention, copper compounds are added to the polish slurry.Type: GrantFiled: February 17, 2000Date of Patent: March 25, 2003Assignee: Applied Materials, Inc.Inventors: Stan D. Tsai, Yuchun Wang, Kapila Wijekoon, Rajeev Bajaj, Fred C. Redeker