Patents by Inventor Kappei IMAMURA

Kappei IMAMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097044
    Abstract: According to one embodiment, a semiconductor device includes a first conductive layer between first and second insulating layers with an oxide semiconductor column extending in the first direction through these layers. A third insulating layer covers the column. The column has a first semiconductor portion at a first position matching the first insulating layer, a second semiconductor portion at a second position matching second insulating layer, and a third semiconductor portion at a third position matching the first conductive layer. The first semiconductor portion is continuous along a second direction between the third insulating layer, the second semiconductor portion is continuous along the second direction between the third insulating layer, but the third semiconductor portion is not continuous between the third insulating layer.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 21, 2024
    Inventors: Yusuke KASAHARA, Kappei IMAMURA, Akifumi GAWASE, Shinji MORI, Akihiro KAJITA
  • Publication number: 20230307520
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming an electrode layer on a film containing indium and etching portions of the electrode layer left exposed by a mask layer until at least a portion of the film is exposed. A spacer film is formed to cover an upper surface of the electrode layer, side surfaces of the electrode layer, and an exposed upper surface of the film. The spacer film on the upper surface of the electrode layer and the exposed upper surface of the film is removed while leaving the spacer film on the side surfaces of the electrode layer. The exposed upper surface of the film is exposed to a reductive gas plasma to reduce portions of the film. These reduced portions of the film are then etched with a chemical solution.
    Type: Application
    Filed: August 29, 2022
    Publication date: September 28, 2023
    Inventors: Takuya KIKUCHI, Yuya NAGATA, Masaya TODA, Kappei IMAMURA, Tsubasa IMAMURA
  • Publication number: 20210288065
    Abstract: A semiconductor storage device of an embodiment includes: a stacked body in which each of a plurality of first conductive layers and each of a plurality of first insulating layers are alternately stacked; a pillar extending in the stacked body in a stacking direction of the stacked body; a plurality of memory cells individually formed at intersections of the plurality of first conductive layers and the pillar; a lower layer structure arranged below the stacked body; a lower receiver that opens on an upper surface of the lower layer structure, the lower receiver having a metal layer filled in a groove extending in a first direction along a surface direction of the upper surface of the lower layer structure; and a strip extending in the first direction and extending in the stacking direction in the stacked body, having a lower end of the strip being arranged in the lower receiver.
    Type: Application
    Filed: September 2, 2020
    Publication date: September 16, 2021
    Applicant: Kioxia Corporation
    Inventor: Kappei IMAMURA
  • Publication number: 20160056165
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes alternately forming plural first insulators and plural first films on a substrate, and etching the first insulators and the first films to form a contact region having first to N-th upper faces whose heights are mutually different where N is an integer of two or more. The method further includes forming a second insulator containing boron or hafnium on the first to N-th upper faces, forming a third insulator on the second insulator, and forming plural electrode layers between the plural first insulators. The method further includes etching the second and third insulators to form first to N-th contact holes respectively reaching the electrode layers under the first to N-th upper faces, and forming first to N-th contact plugs in the first to N-th contact holes respectively.
    Type: Application
    Filed: February 13, 2015
    Publication date: February 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kappei IMAMURA