Patents by Inventor Kar Meng Thong

Kar Meng Thong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for characterizing devices
    Patent number: 9217772
    Abstract: A device characterization system includes a characterization tool and a test flow development generator. The characterization tool is configured to perform testing on a product device according to a test flow and generate test data. The characterization tool includes a list of available test instances that can be performed. The test flow development generator is configured to automatically generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Kar Meng Thong, Alvin L. Calma
  • SYSTEMS AND METHODS FOR CHARACTERIZING DEVICES
    Publication number: 20140040852
    Abstract: A device characterization system includes a characterization tool and a test flow development generator. The characterization tool is configured to perform testing on a product device according to a test flow and generate test data. The characterization tool includes a list of available test instances that can be performed. The test flow development generator is configured to automatically generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kar Meng Thong, Alvin L. Calma
  • Integrated circuit and test method
    Patent number: 8225151
    Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: July 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Kumar Rajeev, Renaud F. H. Gelin, Kar Meng Thong
  • Integrated Circuit and Test Method
    Publication number: 20080282121
    Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.
    Type: Application
    Filed: June 13, 2005
    Publication date: November 13, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Kumar Rajeev, Renaud F.H. Gelin, Kar Meng Thong