Abstract: Techniques are provided for performing bit-locked operations on media. A first control signal is received from a first source, and a second control signal is generated at a second source in response to receiving the first control signal. The media is accessed according to the second control signal. One or more synchronization markers are located during the accessing of the media, and bit-level synchronization between the second source and the media is achieved based, at least partially, on the one or more synchronization markers. A control operation is performed on the media with bit-level synchrony between the second source and the media.

Abstract: Techniques are provided for performing bit-locked operations on media. A first control signal is received from a first source, and a second control signal is generated at a second source in response to receiving the first control signal. The media is accessed according to the second control signal. One or more synchronization markers are located during the accessing of the media, and bit-level synchronization between the second source and the media is achieved based, at least partially, on the one or more synchronization markers. A control operation is performed on the media with bit-level synchrony between the second source and the media.

Abstract: According to the present invention, methods and apparatus are provided for improving the signal quality of received transmission. An adaptive equalizer includes multiple output delay lines. One output delay line is configured to provide gradient elements. Another output delay line is configured with coefficient multipliers calculated using the gradient elements. The coefficient multipliers are used to alter a received signal to more closely correspond to an expected signal. The adaptive equalizer can be used in systems such as optical transceivers.

Abstract: A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the target value by a lookup table or piecewise linear with comparable slopes.

Abstract: A read clock interface includes a serial-to-parallel converter for receiving two interleaved serial data streams read out from a disk and converting the serial data to 17-bit parallel data, and a state machine for receiving a clock signal having a frequency one-half that of a frequency at which the serial data is read out from the disk and frequency dividing the clock signal to generate a conversion clock signal consisting of alternating conversion cycles each having an even number of cycles of the clock signal, wherein the serial-to-parallel converter converts the serial data to parallel data at each conversion cycle of the conversion signal. In the preferred embodiment, the conversion signal consists of alternating conversion cycles of 16 and 18 cycles of the clock signal.

Abstract: The present invention includes a fractional interpretation circuit to be used to correct pre-write compensation for writing data on a disk. The present invention need not be limited to a three phase interpreter but could easily be extended to a 4X or 5X. This could simply be implemented by adding additional current paths from the capacitors to ground in order to incrementally change the slew rate and consequently the phase interpretation.