Abstract: An exemplary embodiment of the present invention sets forth a system, method and computer program product which may include providing an interactive tournament contest; allowing at least one participant participating in the tournament contest to invite at least one additional participant to participate in the tournament contest; and providing a prize to the winner of the interactive tournament contest, wherein a value of the prize increases dependent upon a total number of the participants participating in the tournament contest.

Abstract: An embodiment of the present invention is a technique to provide a secure authentication of chipset configuration. A first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition authenticates and controls enabling a CC functionality. The I/O ME partition manages I/O resources shared with a processor in a secure manner. A second CC register set in a processor interface space provides the CC functionality. The second CC register set includes a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.

Abstract: Apparatus and method are disclosed that control the issuance of posted and non-posted requests. Some embodiments maintain a specified period between successive non-posted requests on a bus. The specific period may be based upon an expected time for a non-posted request to complete on the bus and the configuration of the link.

Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

Abstract: Queue resource sharing for an input/output controller. A shared resource queue is associated with a plurality of ports. The shared resource queue includes a plurality of sections allocated for use by at least one of the plurality of ports based at least in part on a port bandwidth configuration of the plurality of ports.