Patents by Inventor Karan Kacker
Karan Kacker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10591979Abstract: Techniques for battery management of a device having multiple batteries are described herein. In one or more implementations, management for increased battery reliability involves assessing a combination of factors that influence a control policy for multiple batteries in a battery system. Based on the assessment, values of control parameters for power management of the battery system are set to reflect a tradeoff between performance and reliability. Then, at least one of battery utilization or charge current distribution is controlled in dependence upon the values that are set. Control of the battery system can be based in part upon differences in cycle counts for multiple batteries of a battery system for a device, such that cycle counts of the multiple batteries are managed for improved reliability.Type: GrantFiled: April 3, 2015Date of Patent: March 17, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Karan Kacker, Daniel Joseph Dummer, Wei Guo, Stephen Clifford Cooper, Ceceli Ann Wilhelmi, Minsoo Kim
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Publication number: 20160291683Abstract: Techniques for battery management of a device having multiple batteries are described herein. In one or more implementations, management for increased battery reliability involves assessing a combination of factors that influence a control policy for multiple batteries in a battery system. Based on the assessment, values of control parameters for power management of the battery system are set to reflect a tradeoff between performance and reliability. Then, at least one of battery utilization or charge current distribution is controlled in dependence upon the values that are set. Control of the battery system can be based in part upon differences in cycle counts for multiple batteries of a battery system for a device, such that cycle counts of the multiple batteries are managed for improved reliability.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Karan Kacker, Daniel Joseph Dummer, Wei Guo, Stephen Clifford Cooper, Ceceli Ann Wilhelmi, Minsoo Kim
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Patent number: 9099458Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.Type: GrantFiled: July 1, 2012Date of Patent: August 4, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8866026Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 ?m. The platted through hole landing includes an etched pattern and a copper top surface.Type: GrantFiled: August 8, 2012Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8766449Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.Type: GrantFiled: May 24, 2007Date of Patent: July 1, 2014Assignee: Georgia Tech Research CorporationInventors: Suresh K. Sitaraman, Karan Kacker, Thomas Sokol
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Patent number: 8522430Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.Type: GrantFiled: July 14, 2012Date of Patent: September 3, 2013Assignee: International Business Macines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8382489Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.Type: GrantFiled: March 30, 2012Date of Patent: February 26, 2013Assignee: Georgia Tech Research CorporationInventors: Karan Kacker, Suresh K. Sitaraman
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Publication number: 20120299195Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 ?m. The platted through hole landing includes an etched pattern and a copper top surface.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20120279061Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.Type: ApplicationFiled: July 14, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20120267158Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.Type: ApplicationFiled: July 1, 2012Publication date: October 25, 2012Applicant: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8258410Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.Type: GrantFiled: January 26, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8242593Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.Type: GrantFiled: January 27, 2008Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20120192418Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.Type: ApplicationFiled: March 30, 2012Publication date: August 2, 2012Applicant: GEORGIA TECH RESEARCH CORPORATIONInventors: Karan Kacker, Suresh K. Sitaraman
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Patent number: 8206160Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.Type: GrantFiled: May 13, 2008Date of Patent: June 26, 2012Assignee: Georgia Tech Research CorporationInventors: Karan Kacker, Suresh K. Sitaraman
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Publication number: 20090189290Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.Type: ApplicationFiled: January 27, 2008Publication date: July 30, 2009Applicant: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20090188705Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.Type: ApplicationFiled: January 26, 2008Publication date: July 30, 2009Applicant: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20090189289Abstract: A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via.Type: ApplicationFiled: January 27, 2008Publication date: July 30, 2009Applicant: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20080305653Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.Type: ApplicationFiled: May 13, 2008Publication date: December 11, 2008Inventors: Karan Kacker, Suresh K. Sitaraman
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Publication number: 20080245559Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.Type: ApplicationFiled: May 24, 2007Publication date: October 9, 2008Inventors: Suresh K. Sitaraman, Karan Kacker, Thomas Sokol