Patents by Inventor Karan Vaity

Karan Vaity has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LINEARIZATION OF DELAY DOMAIN ANALOG-TO-DIGITAL CONVERTERS
    Publication number: 20260155832
    Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.
    Type: Application
    Filed: January 21, 2026
    Publication date: June 4, 2026
    Inventors: Mishab I, Viswanathan Nagarajan, Himanshu Varshney, Mujammil Patel, Karan Vaity
  • Linearization of delay domain analog-to-digital converters
    Patent number: 12542563
    Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: February 3, 2026
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mishab I, Viswanathan Nagarajan, Himanshu Varshney, Mujammil Patel, Karan Vaity
  • LINEARIZATION OF DELAY DOMAIN ANALOG-TO-DIGITAL CONVERTERS
    Publication number: 20250309913
    Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 2, 2025
    Inventors: Mishab I, Viswanathan Nagarajan, Himanshu Varshney, Mujammil Patel, Karan Vaity