Abstract: Processing circuitry performs a processing operation to generate a two's complement result value representing a positive or negative number in two's complement representation. Normalization-and-rounding circuitry converts the two's complement result value to a normalized-and-rounded floating-point result value represented using sign-magnitude representation. The normalization-and-rounding circuitry comprises incrementing circuitry to perform an increment addition (e.g. a rounding increment or a conversion increment) to generate a fraction of the normalized-and-rounded floating-point result value. For an operation where the increment addition is required to be performed, tininess detection circuitry detects the after-rounding tininess status based on a still-to-be-incremented version of the normalized-and-rounded floating-point result value prior to the increment addition by the increment circuitry.

Abstract: A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.

Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.

Abstract: An apparatus is provided comprising rewritable storage circuitry to store at least one mapping between at least one instruction identifier and a behaviour modification. Selection circuitry selects, from the rewritable storage circuitry, a selected mapping having an instruction identifier that identifies a received instruction. The received instruction causes a data processing unit to perform a default behaviour. Control circuitry causes the data processing unit to behave in accordance with the default behaviour modified by the behaviour modification.

Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P?3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.

Abstract: A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.

Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P?3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.

Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.

Abstract: An apparatus is provided comprising rewritable storage circuitry to store at least one mapping between at least one instruction identifier and a behaviour modification. Selection circuitry selects, from the rewritable storage circuitry, a selected mapping having an instruction identifier that identifies a received instruction. The received instruction causes a data processing unit to perform a default behaviour. Control circuitry causes the data processing unit to behave in accordance with the default behaviour modified by the behaviour modification.