Patents by Inventor Karel J. E. Van Eerdewijk

Karel J. E. Van Eerdewijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testable carriers for integrated circuits
    Patent number: 4879717
    Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: November 7, 1989
    Assignee: U.S. Philips Corp.
    Inventors: Wilhelm A. Sauerwald, Johannes DeWilde, Karel J. E. Van Eerdewijk, Franciscus P. M. Beenker, Marinus T. M. Segers
  • Integrated circuits, carriers therefor and testing apparatus and method for the foregoing
    Patent number: 4791358
    Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.
    Type: Grant
    Filed: September 2, 1986
    Date of Patent: December 13, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Wilhelm A. Sauerwald, Johannes De Wilde, Karel J. E. Van Eerdewijk, Franciscus P. M. Beenker, Marinus T. M. Segers