Abstract: A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.