Abstract: The invention performs very fast switching between a main module and a standby module in the event of module failure. A single control line has different logic level signals applied thereto in the event of a main module failure and a standby module failure, with the signals on the control line being utilized to efficiently switch the on-line status of the modules to a desired state.

Abstract: The invention provides a method and apparatus for controlling the timing at a receiving station for the receipt of asynchronous data transmitted with a time-stamp. The received data is passed through a buffer to the remainder of the station. A decoder at the receiving station generates an indication of buffer fill level and a local time-stamp is also generated. The output timing for the buffer is controlled by a circuit which is responsive to both a difference value off, received and locally generated time-stamps and to the fill level indication.