Patents by Inventor Karen Darbinyan
Karen Darbinyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527298Abstract: An on-chip memory diagnostic (OCMD) circuit may instruct a set of built-in self-test (BIST) engines to execute BIST on memories associated with the set of BIST engines. Next, results of executing BIST on the memories may be received from the set of BIST engines. A set of memory failures may then be identified in the memories based on the results. Next, one or more BIST engines in the set of BIST engines may be instructed to collect diagnostic data for each memory failure. A set of diagnostic data may then be received for the set of memory failures. Next, the set of diagnostic data may be stored in an on-chip data container. The set of diagnostic data may then be provided via a communication channel.Type: GrantFiled: January 29, 2021Date of Patent: December 13, 2022Assignee: Synopsys, Inc.Inventors: Karen Darbinyan, Tatevik Melkumyan, Yervant Zorian
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Patent number: 9541591Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.Type: GrantFiled: August 10, 2015Date of Patent: January 10, 2017Assignee: Synopsys, Inc.Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
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Patent number: 9514258Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.Type: GrantFiled: June 22, 2012Date of Patent: December 6, 2016Assignee: Synopsys, Inc.Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Patent number: 9336342Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.Type: GrantFiled: September 23, 2011Date of Patent: May 10, 2016Assignee: Synopsys, Inc.Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
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Publication number: 20160041212Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.Type: ApplicationFiled: August 10, 2015Publication date: February 11, 2016Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
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Publication number: 20130346056Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: SYNOPSYS, INC.Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Publication number: 20130080847Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: SYNOPSYS, INC.Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
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Patent number: 8295108Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.Type: GrantFiled: January 21, 2011Date of Patent: October 23, 2012Assignee: Synopsys, Inc.Inventors: Karen Darbinyan, Gevorg Torjyan, Yervant Zorian, Mher Mkhoyan
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Publication number: 20110119531Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.Type: ApplicationFiled: January 21, 2011Publication date: May 19, 2011Applicant: SYNOPSYS, INC.Inventors: Karen Darbinyan, Gevorg Torjyan, Yervant Zorian, Mher Mkhoyan
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Patent number: 7898882Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.Type: GrantFiled: June 22, 2007Date of Patent: March 1, 2011Assignee: Synopsys, Inc.Inventors: Karen Darbinyan, Gevorg Torjyan, Yervant Zorian, Mher Mkhoyan
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Patent number: 7673264Abstract: An intellectual property (IP) integrity verification system and method operable with respect to integrating an IP design into a user's embedded IC design. In one embodiment, the IP design is partitioned into a plurality of IP modules based on the requirements of the embedded IC design. For each IP module, a corresponding integrity checker module is provided, wherein each integrity checker module has a port-wise correspondence with its corresponding IP module. The embedded IC design is simulated with the integrity checker modules rather than the IP modules for generating a netlist, which may be verified with respect to any interconnectivity errors associated with the IP modules.Type: GrantFiled: April 5, 2007Date of Patent: March 2, 2010Assignee: Virage Logic Corp.Inventors: Karen Darbinyan, Hayk Chukhajyan, Albert Harutyunyan, Yervant Zorian
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Patent number: 7415640Abstract: Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.Type: GrantFiled: October 13, 2003Date of Patent: August 19, 2008Assignee: Virage Logic CorporationInventors: Yervant Zorian, Gevorg Torjyan, Karen Darbinyan
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Publication number: 20080008015Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.Type: ApplicationFiled: June 22, 2007Publication date: January 10, 2008Inventors: Karen Darbinyan, Gevorg Torjyan, Yervant Zorian, Mher Mkhoyan
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Patent number: 7290186Abstract: Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each intelligence wrapper contains control logic to decode a command from the processor. Each intelligence wrapper contains logic to execute a set of test vectors on a bounded memory. The processor sends a command based self-test to each intelligence wrapper at a first clock speed and the control logic executes the operations associated with that command at a second clock speed asynchronous with the first speed. The processor loads the command containing representations of a march element and data to one or more of the intelligence wrappers via a serial bus.Type: GrantFiled: September 16, 2003Date of Patent: October 30, 2007Assignee: Virage Logic CorporationInventors: Yervant Zorian, Gevorg Torjyan, Karen Darbinyan, Albert Harutyunyan
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Patent number: 7149924Abstract: In general, various methods, apparatuses, and systems in which a processor that contains self test and repair instructions to be executed on a memory is coupled to a first external pin. Assertion of a signal on the first external pin activates execution of the self-test and repair instructions on the memory.Type: GrantFiled: September 5, 2002Date of Patent: December 12, 2006Assignee: Virage Logic CorporationInventors: Yervant Zorian, Gevorg Toriyan, Karen Darbinyan