Patents by Inventor Karen Frida Yorav
Karen Frida Yorav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230179573Abstract: A method, computer system, and a computer program product for determining a cluster connectivity is provided. The present invention may first include receiving as input a connectivity graph. The present invention may then include generating a minimal list of firewall rules from the received connectivity graph by iteratively merging firewall rules with commonality of connectivity attribute.Type: ApplicationFiled: December 7, 2021Publication date: June 8, 2023Inventors: ADI SOSNOVICH, Ziv Nevo, Gil Eliezer Shurek, SHAI DORON, Karen Frida Yorav
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Patent number: 11321792Abstract: A method, product and system including obtaining metadata associated with at least one plugin of a runtime environment, wherein the runtime environment is configured to provide a service to a client, wherein the plugin is configured to measure or enforce metrics of the service; obtaining user selections regarding the metrics, wherein the user selections comprise constraints on the runtime environment; obtaining, based on the metadata of the plugin and based on the user selections, corresponding clauses textually describing the constraints; generating a contract, wherein the contract comprises the corresponding clauses; automatically generating a configuration file based on the user selections; and automatically enforcing the contract by: activating the runtime environment, loading the service in the runtime environment, configuring the plugin according to the configuration file, executing the plugin to identify a violation of the contract, and executing a client function of the client.Type: GrantFiled: August 25, 2020Date of Patent: May 3, 2022Assignee: International Business Machines CorporationInventors: Sima Nadler, Ziv Nevo, Karen Frida Yorav, Roee Shlomo, Tomer Solomon
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Publication number: 20220067858Abstract: A method, product and system including obtaining metadata associated with at least one plugin of a runtime environment, wherein the runtime environment is configured to provide a service to a client, wherein the plugin is configured to measure or enforce metrics of the service; obtaining user selections regarding the metrics, wherein the user selections comprise constraints on the runtime environment; obtaining, based on the metadata of the plugin and based on the user selections, corresponding clauses textually describing the constraints; generating a contract, wherein the contract comprises the corresponding clauses; automatically generating a configuration file based on the user selections; and automatically enforcing the contract by: activating the runtime environment, loading the service in the runtime environment, configuring the plugin according to the configuration file, executing the plugin to identify a violation of the contract, and executing a client function of the client.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Sima Nadler, Ziv Nevo, Karen Frida Yorav, ROEE SHLOMO, Tomer Solomon
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Patent number: 8683441Abstract: Two programs are checked for equivalence. Based on concrete states, a control path in each program is determined. A symbolic representation of the output is determined for each program and verified that for every input that would execute the programs on the determined control paths, the outputs are the same. Based on this operation, iterative processing may be performed to verify equivalence for all inputs of the program.Type: GrantFiled: February 14, 2011Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Sharon Keidar-Barner, Karen Frida Yorav
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Patent number: 8539403Abstract: A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.Type: GrantFiled: July 3, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Eli Arbel, Cynthia Rae Eisner, Oleg Rokhlenko, Karen Frida Yorav
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Patent number: 8453082Abstract: Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.Type: GrantFiled: September 8, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Sharon Keidar-Barner, Ohad Shacham, Karen Frida Yorav
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Publication number: 20130007683Abstract: A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.Type: ApplicationFiled: July 3, 2011Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Eli Arbel, Cynthia Rae Eisner, Oleg Rokhlenko, Karen Frida Yorav
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Publication number: 20120060064Abstract: Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: International Business Machines CorporationInventors: Sharon Keidar-Barner, Ohad Shacham, Karen Frida Yorav
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Patent number: 8086972Abstract: A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit.Type: GrantFiled: July 17, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Cynthia Rae Eisner, Karen Frida Yorav
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Publication number: 20110138362Abstract: Two programs are checked for equivalence. Based on concrete states, a control path in each program is determined. A symbolic representation of the output is determined for each program and verified that for every input that would execute the programs on the determined control paths, the outputs are the same. Based on this operation, iterative processing may be performed to verify equivalence for all inputs of the program.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Sharon Keidar-Barner, Karen Frida Yorav
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Publication number: 20100017764Abstract: A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit.Type: ApplicationFiled: July 17, 2008Publication date: January 21, 2010Inventors: Cynthia Rae Eisner, Karen Frida Yorav
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Publication number: 20090307204Abstract: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Inventors: Ohad Shacham, Karen Frida Yorav
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Patent number: 7401305Abstract: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system.Type: GrantFiled: July 11, 2005Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Ohad Shacham, Karen Frida Yorav