Patents by Inventor Karen Frida Yorav

Karen Frida Yorav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230179573
    Abstract: A method, computer system, and a computer program product for determining a cluster connectivity is provided. The present invention may first include receiving as input a connectivity graph. The present invention may then include generating a minimal list of firewall rules from the received connectivity graph by iteratively merging firewall rules with commonality of connectivity attribute.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: ADI SOSNOVICH, Ziv Nevo, Gil Eliezer Shurek, SHAI DORON, Karen Frida Yorav
  • Patent number: 11321792
    Abstract: A method, product and system including obtaining metadata associated with at least one plugin of a runtime environment, wherein the runtime environment is configured to provide a service to a client, wherein the plugin is configured to measure or enforce metrics of the service; obtaining user selections regarding the metrics, wherein the user selections comprise constraints on the runtime environment; obtaining, based on the metadata of the plugin and based on the user selections, corresponding clauses textually describing the constraints; generating a contract, wherein the contract comprises the corresponding clauses; automatically generating a configuration file based on the user selections; and automatically enforcing the contract by: activating the runtime environment, loading the service in the runtime environment, configuring the plugin according to the configuration file, executing the plugin to identify a violation of the contract, and executing a client function of the client.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sima Nadler, Ziv Nevo, Karen Frida Yorav, Roee Shlomo, Tomer Solomon
  • Publication number: 20220067858
    Abstract: A method, product and system including obtaining metadata associated with at least one plugin of a runtime environment, wherein the runtime environment is configured to provide a service to a client, wherein the plugin is configured to measure or enforce metrics of the service; obtaining user selections regarding the metrics, wherein the user selections comprise constraints on the runtime environment; obtaining, based on the metadata of the plugin and based on the user selections, corresponding clauses textually describing the constraints; generating a contract, wherein the contract comprises the corresponding clauses; automatically generating a configuration file based on the user selections; and automatically enforcing the contract by: activating the runtime environment, loading the service in the runtime environment, configuring the plugin according to the configuration file, executing the plugin to identify a violation of the contract, and executing a client function of the client.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Sima Nadler, Ziv Nevo, Karen Frida Yorav, ROEE SHLOMO, Tomer Solomon
  • Patent number: 8683441
    Abstract: Two programs are checked for equivalence. Based on concrete states, a control path in each program is determined. A symbolic representation of the output is determined for each program and verified that for every input that would execute the programs on the determined control paths, the outputs are the same. Based on this operation, iterative processing may be performed to verify equivalence for all inputs of the program.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sharon Keidar-Barner, Karen Frida Yorav
  • Patent number: 8539403
    Abstract: A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.
    Type: Grant
    Filed: July 3, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eli Arbel, Cynthia Rae Eisner, Oleg Rokhlenko, Karen Frida Yorav
  • Patent number: 8453082
    Abstract: Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sharon Keidar-Barner, Ohad Shacham, Karen Frida Yorav
  • Publication number: 20130007683
    Abstract: A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.
    Type: Application
    Filed: July 3, 2011
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Eli Arbel, Cynthia Rae Eisner, Oleg Rokhlenko, Karen Frida Yorav
  • Publication number: 20120060064
    Abstract: Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: International Business Machines Corporation
    Inventors: Sharon Keidar-Barner, Ohad Shacham, Karen Frida Yorav
  • Patent number: 8086972
    Abstract: A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Cynthia Rae Eisner, Karen Frida Yorav
  • Publication number: 20110138362
    Abstract: Two programs are checked for equivalence. Based on concrete states, a control path in each program is determined. A symbolic representation of the output is determined for each program and verified that for every input that would execute the programs on the determined control paths, the outputs are the same. Based on this operation, iterative processing may be performed to verify equivalence for all inputs of the program.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sharon Keidar-Barner, Karen Frida Yorav
  • Publication number: 20100017764
    Abstract: A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 21, 2010
    Inventors: Cynthia Rae Eisner, Karen Frida Yorav
  • Publication number: 20090307204
    Abstract: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 10, 2009
    Inventors: Ohad Shacham, Karen Frida Yorav
  • Patent number: 7401305
    Abstract: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ohad Shacham, Karen Frida Yorav