Patents by Inventor Karen Lee DELK
Karen Lee DELK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11380618Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.Type: GrantFiled: February 2, 2018Date of Patent: July 5, 2022Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
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Patent number: 11152139Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.Type: GrantFiled: July 16, 2018Date of Patent: October 19, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Sharrone Rena Smith
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Publication number: 20210167013Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.Type: ApplicationFiled: February 13, 2021Publication date: June 3, 2021Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk
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Patent number: 10923425Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.Type: GrantFiled: January 17, 2018Date of Patent: February 16, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
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Publication number: 20200020464Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.Type: ApplicationFiled: July 16, 2018Publication date: January 16, 2020Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk, Sharrone Rena Smith
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Patent number: 10452803Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.Type: GrantFiled: January 27, 2017Date of Patent: October 22, 2019Assignee: ARM LimitedInventor: Karen Lee Delk
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Patent number: 10417371Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.Type: GrantFiled: January 27, 2017Date of Patent: September 17, 2019Assignee: ARM LimitedInventors: Karen Lee Delk, Marlin Wayne Frederick, Jr., Ravindra Narayana Rao
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Publication number: 20190244900Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.Type: ApplicationFiled: February 2, 2018Publication date: August 8, 2019Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk
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Patent number: 10210303Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.Type: GrantFiled: January 27, 2017Date of Patent: February 19, 2019Assignee: ARM LimitedInventors: Ravindra Narayana Rao, Marlin Wayne Frederick, Jr., Karen Lee Delk, Stefan Charles Creaser
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Publication number: 20180218108Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus may include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first and second segments. The apparatus may include a stitcher module that performs sleep signal stitching for the integrated circuit by distributing a sleep signal from the control pin to the power gates that includes each power gate in each of the first, second, and third segments.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Inventors: Ravindra Narayana Rao, Marlin Wayne Frederick, JR., Karen Lee Delk, Stefan Charles Creaser
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Publication number: 20180218106Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Inventor: Karen Lee Delk
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Publication number: 20180218107Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Inventors: Karen Lee Delk, Marlin Wayne Frederick, JR., Ravindra Narayana Rao
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Publication number: 20180211914Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.Type: ApplicationFiled: January 17, 2018Publication date: July 26, 2018Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk
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Patent number: 9892220Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: GrantFiled: March 13, 2017Date of Patent: February 13, 2018Assignee: ARM LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen, James Dennis Dodrill
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Publication number: 20170185709Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Marlin Wayne FREDERICK, JR., Karen Lee DELK, Lena AHLEN, James Dennis DODRILL
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Patent number: 9690889Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: GrantFiled: August 18, 2016Date of Patent: June 27, 2017Assignee: ARM LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen, James Dennis Dodrill
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Patent number: 9653413Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.Type: GrantFiled: June 18, 2014Date of Patent: May 16, 2017Assignee: ARM LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
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Publication number: 20160357894Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: ApplicationFiled: August 18, 2016Publication date: December 8, 2016Inventors: Marlin Wayne FREDERICK, JR., Karen Lee DELK, Lena AHLEN, James Dennis DODRILL
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Publication number: 20150371959Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Marlin Wayne FREDERICK, JR., Karen Lee DELK