Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

Abstract: A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.

Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

Abstract: A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.

Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.