Abstract: Hierarchical congestion identification and control hardware supports multi-level congestion control at flow, tenant and virtual machine (VM) levels. Hardware implementation expedites response to congestion notifications and frees-up processor bandwidth. A hierarchy of transmit shapers in a transmit ring scheduler isolate rate adjustments for flows, tenants and VMs. The hierarchy of shapers provide a hierarchy of congestion control nodes to control flows and aggregate flows. Hardware quickly associates congested flows with shapers before or after receiving a congestion notification. The associations may be used by any flow control algorithm to selectively rate-control shapers to control flow rates. Shaper associations and configured states, scheduler configuration, congestion states, thresholds and other flow information may be stored and monitored to filter data flows that need attention and to raise alerts at flow, tenant and VM levels.

Abstract: A memory access circuit and a corresponding method are provided. The memory access circuit includes a crypto block in communication with a memory that encrypts data of a data block on a block basis. The memory access circuit also includes a fault injection block configured to inject faults to the data in the data block. The memory access circuit further includes a data scrambler and an address scrambler. The data scrambler is configured to scramble data in the memory by shuffling data bits within the data block in a plurality of rounds and mash the shuffled data bits with random data. The address scrambler is configured to distribute the scrambled data across the memory. A memory system including the memory access circuit is also disclosed to implement the corresponding method.

Abstract: Hierarchical congestion identification and control hardware supports multi-level congestion control at flow, tenant and virtual machine (VM) levels. Hardware implementation expedites response to congestion notifications and frees-up processor bandwidth. A hierarchy of transmit shapers in a transmit ring scheduler isolate rate adjustments for flows, tenants and VMs. The hierarchy of shapers provide a hierarchy of congestion control nodes to control flows and aggregate flows. Hardware quickly associates congested flows with shapers before or after receiving a congestion notification. The associations may be used by any flow control algorithm to selectively rate-control shapers to control flow rates. Shaper associations and configured states, scheduler configuration, congestion states, thresholds and other flow information may be stored and monitored to filter data flows that need attention and to raise alerts at flow, tenant and VM levels.

Abstract: A memory access circuit and a corresponding method are provided. The memory access circuit includes a crypto block in communication with a memory that encrypts data of a data block on a block basis. The memory access circuit also includes a fault injection block configured to inject faults to the data in the data block. The memory access circuit further includes a data scrambler and an address scrambler. The data scrambler is configured to scramble data in the memory by shuffling data bits within the data block in a plurality of rounds and mash the shuffled data bits with random data. The address scrambler is configured to distribute the scrambled data across the memory. A memory system including the memory access circuit is also disclosed to implement the corresponding method.