Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: A device made through a fabrication method is disclosed. In one embodiment, the method includes a dry etch plasma process that utilizes CO2 to etch a layer. Furthermore, the dry etch plasma process may utilize CO2 in combination with NH3, H2, Ar, N2, He, or other inert gases during the etching process. In another embodiment, the CO2 dry etch plasma process etches an anti-reflectant coating layer while enabling greater selectivity and control with regard to underlying layers.

Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.

Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.

Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.