Abstract: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

Abstract: What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a timing budget by examining said estimated arrival times at said block pins.