Abstract: A sports or fitness training pole, such as a pole used in Nordic walking, roller skating or skiing, including a pole shaft, a grip fixed to the top end of the pole shaft, and a ring construction fixed to the bottom end of the pole shaft, where the pole shaft includes two curved parts curving in opposite directions. The first curved part is in the central region of the pole and the second curved part is between the first curved part and the grip, and with respect to a straight line passing through the first curved part and the grip, the pole shaft above the first curved part is located on the rear side of the straight line, while the grip is in a forward tilted position with respect to the straight line.

Abstract: A sports or fitness training pole, such as a pole used in Nordic walking, roller skating or skiing, including a pole shaft, a grip fixed to the top end of the pole shaft, and a ring construction fixed to the bottom end of the pole shaft, where the pole shaft includes two curved parts curving in opposite directions. The first curved part is in the central region of the pole and the second curved part is between the first curved part and the grip, and with respect to a straight line passing through the first curved part and the grip, the pole shaft above the first curved part is located on the rear side of the straight line, while the grip is in a forward tilted position with respect to the straight line.

Abstract: A temperature compensated frequency reference comprising first MEMS oscillator (MEMS1) used as frequency reference oscillator (REF) for phase locked loop, and means for temperature compensation of phase locked loop output frequency (Fout), wherein the phase locked loop comprises a second MEMS oscillator (MEMS2) used as electronically controlled oscillator (VCO) of phase locked loop.

Abstract: The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters.

Abstract: The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.

Abstract: Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.

Abstract: Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency.

Abstract: An IC multiplier circuit has four cells having bipolar transistors to give an exponential input-output function. Each cell has a squaring bipolar transistor and an emitter follower. Differential output signals are taken from the squaring bipolar transistor. The voltage follower is an emitter follower with the bias current through it is substantially larger, e.g. about 10 times larger, than the bias current through the squaring bipolar transistor, which has an emitter resistor.

Abstract: A delta-sigma modulator for converting an analog input signal into a digital output signal comprises a modulator input (501) and a first analog to digital converter (504) coupled to the modulator input (501). The first analog to digital converter has a first analog input and a first digital output. The delta-sigma modulator further comprises an error quantization unit (505, 506, 507) coupled to the first digital output for determining the quantization error caused by the first analog to digital converter (504). Additionally it comprises first signal combining means (508, 708, 802) for combining the outputs of the first analog to digital converter and said error quantization unit to form the digital output signal.